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Semiconductor device having an improved immunity to a short-circuit at a power supply line

  • US 5,519,650 A
  • Filed: 09/07/1994
  • Issued: 05/21/1996
  • Est. Priority Date: 09/29/1993
  • Status: Expired due to Fees
First Claim
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1. A semiconductor memory device comprising:

  • a memory array having a plurality of memory cells arranged in rows and columns;

    a plurality of conductive lines arranged extending in parallel with each other over said memory array;

    a plurality of isolation means provided for each of said plurality of conductive lines, each of said plurality of isolation means dividing a corresponding conductive line into at least two segments upon isolation of the corresponding conductive line; and

    a column decoder for generating a column select signal for designating a column among said columns in said memory array, wherein said plurality of conductive lines includes conductor lines provided corresponding to respective outputs of said column decoder to transfer column select signal generated at corresponding outputs of said column decoder.

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