Semiconductor device having an improved immunity to a short-circuit at a power supply line

• US 5,519,650 A
• Filed: 09/07/1994
• Issued: 05/21/1996
• Est. Priority Date: 09/29/1993
• Status: Expired due to Fees

• Current Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation), Mitsubshi Electric Engineering Company Limited (Mitsubishi Electric Corporation)
• Original Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation), Mitsubishi Electric Engineering Co Ltd (Mitsubishi Electric Corporation)
• Inventors: Sakurai, Mikio, Mori, Shigeru, Sakemi, Kazuhiro, Ichimura, Tooru
• Primary Examiner(s): Popek, Joseph A.
• Application Number:
  US08/301,752
• Time in Patent Office: 622 Days
• Field of Search: 365/51, 365/63, 365/200, 365/226
• US Class Current: 365/63
• CPC Class Codes: G11C 29/50 Marginal testing, e.g. race, voltage or current testing
• CPC Class Codes: H01L 23/5258 the change of state resulting from the use of an external beam, e.g. laser beam or ion beam
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A semiconductor memory device includes a memory cell array (1) having a plurality of memory cells arranged in rows and columns, a plurality of column select lines (3) extending over the memory cell array and coupled to received column select signals generated by a column decoder (100), a plurality of power supply lines (4) provided in parallel with the column select lines to transfer a power supply voltage from a main power supply line (130), and a plurality of ground lines (5) provided in parallel with the column select lines to transfer a ground voltage from a main ground line. A plurality of fuse elements (6) are provided for each of the column select lines. When a short-circuit is found between a column select line and power supply line or a ground line, a fuse element corresponding to the short-circuited column select line is blown off and the short-circuited column select line is isolated from the column decoder. By repairing the short-circuited column select line with a redundant column select line (60), the memory device operates correctly without an adverse effect of the short-circuit.

Claims

1. A semiconductor memory device comprising:

a memory array having a plurality of memory cells arranged in rows and columns;

a plurality of conductive lines arranged extending in parallel with each other over said memory array;

a plurality of isolation means provided for each of said plurality of conductive lines, each of said plurality of isolation means dividing a corresponding conductive line into at least two segments upon isolation of the corresponding conductive line; and

a column decoder for generating a column select signal for designating a column among said columns in said memory array, wherein said plurality of conductive lines includes conductor lines provided corresponding to respective outputs of said column decoder to transfer column select signal generated at corresponding outputs of said column decoder.

2. The semiconductor memory device according to claim 1, wherein each of said plurality of isolation means brings one segment among said at least two segments into an electrically floating state when isolating a corresponding conductive line.

3. A semiconductor device according to claim 1, wherein each of said plurality of isolation means is provided at a position near a corresponding output of said column decoder.

4. A semiconductor memory device according to claim 1, further comprising a main conductive line extending along one side of said memory array in a direction crossing said plurality of conductive lines, and wherein said plurality of conductive lines are coupled to said main conductive line, and each of said plurality of isolation means isolates a corresponding conductive line from said main conductive line.

5. A semiconductor memory device according to claim 1, wherein each of said plurality of conductive lines is provided with a second plurality of isolation means.

6. A semiconductor memory device according to claim 5, further comprising an interconnection line extending over said memory array to cross and interconnect said plurality of conductive lines in a predetermined region of said memory array.

7. A semiconductor memory device according to claim 1, wherein said plurality of conductive lines includes,

a first plurality of said conductor lines of column select lines provided corresponding to the respective outputs of said column decoder to transfer a column select signal generated at a corresponding output,

a second plurality of power lines for transferring a first supply voltage, and

a third plurality of source lines for transferring a second supply voltage lower than said first supply voltage.

8. A semiconductor memory device according to claim 7, wherein said plurality of isolation means are provided for said first plurality of column select lines.

9. A semiconductor memory device according to claim 7, wherein said plurality of isolation means are provided for said second plurality of power supply lines and for said third plurality of source lines.

10. A semiconductor memory device according to claim 7, wherein said power lines and said source lines are alternately arranged with a column select line interposed between a power supply line and a source line.

11. A semiconductor memory device according to claim 7, wherein a set of a predetermined number of said power supply lines and a set of the predetermined number of said source lines are alternately arranged, and said conductor lines include a column select line interposed between power supply lines, a column select line between source lines, and a column select line, between a power supply line and a source line.

12. A semiconductor memory device according to claim 7, wherein said power supply lines and said source lines are alternately arranged with plural column select lines interposed between a power supply line and a ground line.

13. A semiconductor memory device according to claim 1, wherein said plurality of conductive lines includes a first plurality of said conductor lines each for transferring a signal, and a second plurality of second conductor lines for transferring a source voltage, said first conductor lines and said second conductor lines being alternately arranged and formed at the same level interconnection layer.

14. A semiconductor memory device, comprising:

a memory cell array including a plurality of memory cells arranged in rows and columns;

a first plurality of power lines provided in parallel with each other and extending over said memory cell array for transferring a power voltage; and

a second plurality of source lines provided in parallel with said power lines and extending over said memory cell array for transferring a source voltage lower than said power voltage;

a set of a predetermined number, greater than one, of said power lines and a set of the predetermined number, greater than one, of said source lines being alternately arranged, wherein

no source line is interposed between the power lines of the set of a predetermined number of said power lines and no power line is interposed between the source lines of the set of a predetermined number of said source lines.

15. A semiconductor memory device comprising:

a memory cell array including a plurality of memory cells arranged in rows and columns;

a plurality of interconnection lines extending over said memory cell array and provided in parallel with each other for transferring a signal; and

a plurality of first and second conductor lines provided in parallel with said plurality of interconnection lines to extend over said memory array for transferring a predetermined first and second constant level voltages, wherein

a multiple, greater than one, of the interconnection lines is interposed between each of the first conductor lines and each of the second conductor lines.

16. A method of repairing a semiconductor memory device including a memory cell array having a plurality of memory cells arranged in rows and columns;

a plurality of first conductor lines extending along the columns over said memory cell array for transferring column select signals, and a plurality of second conductor lines provided in parallel with said first conductor lines and extending over said memory cell array for transferring a predetermined voltage, comprising the steps of;

detecting a short-circuit between a first conductor line among said plurality of first conductor lines and a second conductor line among said plurality of first conductor lines, said first conductor line being adjacent to said second conductor line; and

isolating at least one of said first conductor line and said second conductor line to bring the isolated conductor line into an electrically floating state.