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Architecture for high performance management of multiple circular FIFO storage means

  • US 5,519,701 A
  • Filed: 03/29/1995
  • Issued: 05/21/1996
  • Est. Priority Date: 03/29/1995
  • Status: Expired due to Term
First Claim
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1. In a data communication system handling packet and multimedia data transferred in either direction between a host bus and a network, a queue manager for managing multiple circular FIFO storage means included in the system, comprising:

  • (a) a programmable parameter RAM including a base pointer array, a threshold array, a read pointer array and a write pointer array;

    each array having two sides, one side of each array coupled to an input selector, the other side of each array coupled to a first output selector, the read and write pointer arrays being further coupled to a second output selector;

    (b) computation logic means coupled to the first and second output selectors and including a first calculating means, a second calculating means, and logic means, the first calculating means calculating a queue limit that is the top location of the queue and providing an output signal "qatlim";

    the second calculating means calculating the amount of space remaining in a queue and providing a queue empty signal or a queue at or above threshold signal;

    (c) the logic means coupled to the second calculating means for providing a queue almost full or queue full signal;

    (d) means coupled to the first selector for programming the parameter RAM; and

    (e) status means coupled to the computation logic means for receiving the empty, full, wrapped, almost full, and threshold signals for use by an application running in the system in receiving data from or sending data to the multiple circular FIFO storage means.

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