Ferrelectric adaptive-learning type product-sum operation circuit element and circuit using such element

• US 5,519,812 A
• Filed: 03/05/1993
• Issued: 05/21/1996
• Est. Priority Date: 08/24/1992
• Status: Expired due to Term

• Current Assignee: Tokyo Institute of Technology (National University Corporation Tokyo Institute of Technology)
• Original Assignee: Tokyo Institute of Technology (National University Corporation Tokyo Institute of Technology)
• Inventors: Ishihara, Hiroshi
• Primary Examiner(s): Westin, Edward P.
• Assistant Examiner(s): DRISCOLL, BENJAMIN
• Application Number:
  US08/026,779
• Time in Patent Office: 1,173 Days
• Field of Search: 257/295, 365/145, 307/201, 307/450, 326/112, 395/24
• US Class Current: 706/33
• CPC Class Codes: G06N 3/063 using electronic means
• CPC Class Codes: G06N 3/065 Analogue means

Abstract

The present invention relates to a product-sum operation circuit element and a circuit for addition by weighting a number of signals input in one neuron circuit in a neural network, and can provide an adaptive-learning neuron circuit for changing an interval of output pulses by learning by connecting a simple pulse generating circuit consisting of capacitance, resistance, unijunction transistor and the like.

A product-sum operation circuit element according to the present invention, includes an insulator substrate, a single crystal semiconductor thin film having a p-n-p or n-p-n structure in a lateral direction formed in the shape of stripes on the insulator substrate, a ferroelectric thin film deposited thereon for covering at least the semiconductor stripe structure, and a stripe-like electrode consisting of a metal or a polycrystalline semiconductor further formed thereon for intersecting the semiconductor stripes at a right angle or suitable angle.

Claims

1. A product-sum operation circuit element comprising:

an insulator substrate;

at least one single crystal semiconductor thin film region on the insulator substrate, the at least one single crystal semiconductor thin film region extending in a first direction;

a ferroelectric thin film deposited on the insulator substrate for covering at least the at least one single crystal semiconductor thin film region; and

an electrode, formed on the ferroelectric thin film, the electrode extending in a second direction and crossing the at least one single crystal semiconductor thin film region;

wherein the at least one single crystal semiconductor thin film region includes first, second and third semiconductor thin film sections;

wherein the first and third sections are of a same conductivity-type and the second section is of a conductivity-type which is the opposite of the conductivity-type of the first and third sections; and

wherein the first, second and third semiconductor thin film sections are arranged along the second direction with the second section disposed between the first and third sections.

2. The product-sum operation circuit element according to claim 1, wherein the first and third semiconductor thin film sections are n-type semiconductors and the second semiconductor thin film section is a p-type semiconductor.

3. The product-sum operation circuit element according to claim 1, wherein the first and third semiconductor thin film sections are p-type semiconductors and the second semiconductor thin film section is an n-type semiconductor.

4. An adaptive-type product-sum operation circuit comprising:

an excitatory pulse circuit for producing an excitatory pulse;

an inhibitory pulse circuit for producing an inhibitory pulse; and

an adaptive-learning type product-sum operation circuit element including;

an insulating substrate;

a semiconductor thin film layer formed on the insulating substrate;

a ferroelectric thin film layer, having a residual polarization, formed on the semiconductor thin film layer; and

an electrode formed on the ferroelectric thin film, the electrode being Coupled to receive the excitatory pulse and to receive the inhibitory pulse;

wherein the ferroelectric thin film layer is responsive to the excitory pulse for increasing the residual polarization by a first predetermined amount and is responsive to the excitatory pulse for decreasing the residual polarization by a second predetermined amount;

wherein the semiconductor thin film layer extends in a first direction, and the electrode extends in a second direction and crosses the semiconductor thin film layer;

wherein the semiconductor thin film layer includes first, second and third semiconductor thin film regions;

wherein the first and third regions are of a same conductivity-type and the second region is of a conductivity-type which is the opposite of the conductivity-type of the first and third regions; and

wherein the first, second and third semiconductor thin film regions are arranged along the second direction with the second region disposed between the first and third regions.

5. The adaptive-type product-sum operation circuit according to claim 4, wherein the first and third semiconductor thin film regions are n-type semiconductors and the second semiconductor thin film region is a p-type semiconductor.

6. The adaptive-type product-sum operation circuit according to claim 4, wherein the first and third semiconductor thin film regions are p-type semiconductors and the second semiconductor thin film region is an n-type semiconductor.

7. A semiconductor circuit element comprising:

an insulator substrate;

a plurality of single crystal silicon semiconductor thin film stripes formed on the insulator substrate and extending in parallel fashion in a first direction, each one of said plurality of stripes being comprised of first and second semiconductor regions of a first conductivity-type and a third semiconductor region of a second conductivity-type disposed adjacent to and between said first and second semiconductor regions;

a ferroelectric thin film deposited on the insulator substrate and covering the plurality of single crystal silicon semiconductor thin film stripes; and

a plurality of electrode stripes, formed on the ferroelectric thin film and extending in parallel fashion in a second direction perpendicular to said first direction, each electrode stripe crossing a respective first, second and third semiconductor region of a respective one of the plurality of single crystal silicon semiconductor thin film stripes.

8. The circuit element according to claim 7, wherein the plurality of electrode stripes are electrodes for receiving excitatory pulses from excitatory pulse circuits and for receiving inhibitory pulses from inhibitory pulse circuits, and wherein the ferroelectric thin film is responsive to the excitatory pulses for increasing residual polarization by a first predetermined amount and is responsive to the inhibitory pulses for decreasing the residual polarization by a second predetermined amount, the circuit element thereby being an adaptive-learning type product-sum operation circuit.