Multi instruction register mapper
First Claim
1. Apparatus for mapping logical registers, comprising:
- a map comprising;
means for storing a current set of register numbers which are available for assignment in a current cycle and for storing a previous set of register numbers which were assigned in a previous cycle;
means for storing a current set of logical register destination operands and for storing a previous set of logical register destination operands;
a plurality of register files corresponding to a number of instructions to be mapped in a cycle, said register files each having a plurality of locations, each register file having a plurality of write ports corresponding to said number of instructions to be mapped in a cycle, with said write ports of each of said register files having a write address port and a write data port, and with a first write port of a first one of said register files having the corresponding write address port fed by a first one of the logical destination register operands of a previous set of instructions and the corresponding write data port fed by a first one of the register numbers of the previous set of instructions, and a last write port of a first one of said register files having the corresponding write address port fed by a last one of the logical destination register operands of the previous set of instructions and the corresponding write data port fed by a last one of the register numbers of the previous set of instructions.
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Accused Products
Abstract
A pipelined processor includes an instruction unit including a register mapper, to map register operand fields of a set of instructions and an instruction scheduler, fed by the set of instructions, to reorder the issuance of the set of instructions from the processor. The mapped register operand fields are associated with the corresponding instructions of the reordered set of instructions prior to issuance of the instructions. The processor further includes a branch prediction table which maps a stored pattern of past histories associated with a branch instruction to a more likely prediction direction of the branch instruction. The processor further includes a memory reference tagging store associated with the instruction scheduler so that the scheduler can reorder memory reference instructions without knowing the actual memory location addressed by the memory reference instruction.
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Citations
18 Claims
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1. Apparatus for mapping logical registers, comprising:
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a map comprising; means for storing a current set of register numbers which are available for assignment in a current cycle and for storing a previous set of register numbers which were assigned in a previous cycle; means for storing a current set of logical register destination operands and for storing a previous set of logical register destination operands; a plurality of register files corresponding to a number of instructions to be mapped in a cycle, said register files each having a plurality of locations, each register file having a plurality of write ports corresponding to said number of instructions to be mapped in a cycle, with said write ports of each of said register files having a write address port and a write data port, and with a first write port of a first one of said register files having the corresponding write address port fed by a first one of the logical destination register operands of a previous set of instructions and the corresponding write data port fed by a first one of the register numbers of the previous set of instructions, and a last write port of a first one of said register files having the corresponding write address port fed by a last one of the logical destination register operands of the previous set of instructions and the corresponding write data port fed by a last one of the register numbers of the previous set of instructions. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16)
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17. Apparatus for mapping n logical registers used in the execution of a plurality of instructions, comprising:
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a map comprising; a plurality of register files corresponding to the number of instructions to be mapped in a cycle, said register files each having a plurality of locations, each register file having a like plurality of write ports and three read ports for providing an output from said register file, with said write ports of each of said register files having a write address port and a write data port; means for maintaining a list of locations in each of said register files which are free to be used in a current cycle, said means further comprising; means for storing a current set of register numbers which are available for assignment in the current cycle; means for storing a previous set of register numbers which were assigned in the previous cycle; means for storing a current set of logical register destination operands and for storing a previous set of logical register destination operands; means for providing the previous and current sets of register numbers as data to said register files with a first one of said register files having a first one of said register numbers as data to a first data port of said register file, and each succeeding one of said register files having each succeeding one of said register numbers input as data to a first data port of each of said succeeding files, and for providing the previous and current sets of register operands as addresses to said register files with a first one of said files having a first one of said register operands as an address to a first address port of said first file, and each succeeding one of said files having each succeeding one of said register operands as an address to a first address port of each of said succeeding files; means for providing addresses to said read ports of each of said files to provide at the output of said files a register address corresponding to a physical home of each of said previous logical register destination operands; and means for maintaining a list of each logical register operand which was reassigned in a previous number of cycles. - View Dependent Claims (18)
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Specification