Flash memory system providing both BIOS and user storage capability

• US 5,519,843 A
• Filed: 03/15/1993
• Issued: 05/21/1996
• Est. Priority Date: 03/15/1993
• Status: Expired due to Fees

• Current Assignee: Systems LMP Incorporated
• Original Assignee: Systems LMP Incorporated
• Inventors: Ban, Amir, Levy, Rony, Yurtsev, Anatoly, Mergui, Arie, Moran, Dov, Deitcher, David
• Primary Examiner(s): Ray, Gopal C.
• Application Number:
  US08/031,713
• Time in Patent Office: 1,163 Days
• Field of Search: 395/425, 395/325, 395/800, 395/500, 395/430, 395/412, 395/700, 365/900, 365/218, 365/49, 365/230.03, 364/431.12
• US Class Current: 711/103
• CPC Class Codes: G06F 12/0292 using tables or multilevel address translation means G06F12/023 takes precedence; address translation in virtual memory systems G06F12/10
• CPC Class Codes: G06F 2212/2022 Flash memory

Abstract

A flash memory system having a controller and a flash memory device for providing BIOS, operating system and user storage capabilities is described. According to exemplary embodiments of the present invention, flash memory systems can be designed as integrated circuit packages which are pin compatible with conventional ROM BIOS chips so that existing systems can be readily upgraded without extensive modifications.

Claims

1. A system, comprising:

(a) system memory means for storing user data;

(b) central processing means for providing control functions of said system;

(c) an integrated circuit package; and

(d) a system bus connecting said system memory means to said central processing means and to said integrated circuit package for communicating data between said system memory means, said central processing means and said integrated circuit package;

said integrated circuit package comprising;

(i) flash memory means for storing both BIOS routines and said user data, said flash memory means storing an emulation means for allowing a portion of said flash memory means to emulate a hard disk; and

(ii) controller means connected to said flash memory means for interfacing said flash memory means and said system bus, said controller means including means for intercepting a BIOS boot process to install said emulation means in said system memory.

2. The system of claim 1 wherein:

said controller means provides a window between said flash memory means and said system memory means.

3. The system of claim 2, wherein:

said controller means includes address means for detecting accesses to system memory addresses within said window.

4. The system of claim 3, wherein:

said controller means includes shifting means for shifting said window between different portions of said flash memory means.

5. The system of claim 4, wherein:

said shifting means shifts said window in response to a detection of an access to at least one predetermined system memory address by said address means.

6. The system of claim 5, wherein:

said shifting means shifts said window to a portion of said flash memory means which emulates a hard disk drive in response to a detection of a predetermined sequence of system memory addresses by said address means.

7. The system of claim 1, wherein said intercepting means includes insertion means for inserting a jump-in-place instruction into one of said BIOS routines in response to a system reset.

8. The system of claim 7, wherein:

said intercepting means further comprises detecting means for detecting when said jump-in-place instruction has been executed a predetermined number of consecutive times.

9. The system of claim 8, wherein:

said insertion means causes said central processing means to jump to an address in said flash memory means in response to a result of said detecting means, whereby said emulation means is loaded into said system memory.

10. The system of claim 9, wherein:

said central processing means completes said one of said BIOS routines after said emulation means has been loaded into said system memory.

11. The system of claim 1, wherein said emulation means replaces original hardware interrupt vectors of said system with vectors pointing to a subroutine in said emulation means.

12. The system of claim 1, wherein said emulation means controls reading, waiting, and erasing of said portion of said flash memory means.

13. An integrated circuit package, comprising:

(i) flash memory means for storing both BIOS routines and user data, said flash memory means storing emulation means for allowing a portion of said flash memory means to emulate a hard disk;

(ii) controller means connected to said flash memory means for controlling access to said flash memory means, said controller means including means for intercepting a BIOS boot process to install said emulation means in said system memory; and

(iii) pin means connected to said flash memory means and to said controller means for providing external connections to the integrated circuit package.

14. The integrated circuit package of claim 13, wherein:

said intercepting means includes insertion means for inserting a jump-in-place instruction into one of said BIOS routines in response to a system reset received by said pin means.

15. The integrated circuit package of claim 14, wherein:

said intercepting means further comprises detecting means for detecting when said jump-in-place instruction has been executed a predetermined number of consecutive times.

16. A memory system for computers, comprising:

(a) a flash memory device that is divided into at least two portions, a first portion of said flash memory device storing low-level service routines for the operation of a computer, and a second portion of said flash memory device being configured to store user-designated information, said second portion of the flash memory device including a first block of memory which stores a flash file management system, and at least one other block of memory which is adapted to store user-designated data; and

(b) a controller connected to said flash memory device which operates as an interface between said flash memory device and an associated computer system, said controller including;

(i) windowing means for mapping external addresses of the associated computer system to addresses in a selected portion of said flash memory device, to thereby establish a window to said selected portion of said flash memory device, and

(ii) means responsive to memory accesses by the computer system for switching the selected portion of said flash memory device between said first and second portions.

17. The memory system of claim 16 wherein said switching means is responsive to a command to reset the computer system to cause said windowing means to first establish a window to said first portion of said flash memory device to enable said low-level service routines to be booted therefrom, and wherein said controller includes means for causing said switching means to switch the selected portion to said first block in said second portion of the memory device at a predetermined point in the booting of said low-level service routines, to enable said flash file management system to be accessed during a reset procedure.

18. The memory system of claim 16 wherein said switching means is responsive to an access to a predetermined address by the computer system to switch the selected portion to said first portion, and is responsive to consecutive accesses to a predetermined sequence of plural addresses to switch the selected portion to said second portion of the flash memory device.