Method of pipelining sequential writes in a flash memory

• US 5,519,847 A
• Filed: 06/30/1993
• Issued: 05/21/1996
• Est. Priority Date: 06/30/1993
• Status: Expired due to Term

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Rozman, Rodney R., Fandrich, Mickey L., Durante, Richard J.
• Primary Examiner(s): Kim, Matthew M.
• Application Number:
  US08/085,969
• Time in Patent Office: 1,056 Days
• Field of Search: 364/200 MS File, 364/900 MS File, 365/230.08, 365/230.09, 365/900, 395/425, 395/428-430, 395/467, 395/496, 395/550
• US Class Current: 711/169
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 7/1039 using pipelining techniques, i.e. using latches between functional memory parts, e.g. row/column decoders, I/O buffers, sense amplifiers

Abstract

A method of increasing the data throughput of a memory device including a page buffer. Data throughput is increased by pipelining write operations such that one plane of the page buffer is being used to program the memory array of the device while the other plane of the page buffer is being loaded with data to be used in the next program operation. The first write operation is set up by loading a first block of data in to the first plane of the page buffer. In the following clock cycle, the first operation begins by commanding the memory device to program the memory array with the first block of data stored in the first plane. The second write operation is setup immediately following the first command to program. The second write operation is setup by loading a second block of data into the second plane of the page buffer. Loading of the second plane occurs while the memory array is being programmed from the first plane. The second write operation begins by commanding the array controller to program the flash memory array with the second block of data stored in the second plane.

Claims

1. A method of increasing data throughput of a flash memory device including a flash memory array, an array controller and a page buffer, the page buffer including a first plane and a second plane, the array controller controlling a programming of the flash memory array, the array controller being coupled to the page buffer, the method comprising the steps of:

a) loading the first plane with a first byte of data;

b) commanding the array controller to program the flash memory array with the first byte of data stored in the first plane;

c) loading the second plane with a second byte of data while the array controller is programming the flash memory array with the first byte of data stored in the first plane; and

d) commanding the array controller to program the flash memory array with the second byte of data stored in the second plane.

2. The method of claim 1 further comprising the step of:

a) first determining whether a plane of the page buffer is available for user access.

3. The method of claim 2 wherein the step of determining whether a plane is available includes reading a status register of the flash memory array.

4. The method of claim 1 wherein the first plane and the second plane of the page buffer comprise static random access memory.

5. The method of claim 1 wherein step c) occurs in a clock cycle immediately following step b).

6. The method of claim 5 wherein the first plane and the second plane of the page buffer comprise static random access memory.

7. A computer implemented method of increasing data throughput of a flash memory device, the flash memory device including a flash memory array, an array controller and a page buffer, the page buffer including a first plane and a second plane, the array controller controlling a programming of the flash memory array, the array controller being coupled to the page buffer, the method comprising the computer implemented steps of:

a) loading the first plane with a byte of data by coupling a first set of data signals to the flash memory device;

b) commanding the array controller to program the flash memory array with the first byte of data stored in the first plane by coupling command signals to the flash memory device representing a command to program from the page buffer;

c) while the array controller is programming the flash memory array, loading the second plane with a block of data by coupling data signals representing the block of data to the flash memory device; and

d) commanding the array controller to program the flash memory array with the block of data stored in the second plane by coupling command signals to the flash memory device representing a command to program from the page buffer.

8. The method of claim 7 further comprising the step of:

a) first determining whether a plane of the page buffer is available.

9. The method of claim 8 wherein the step of determining whether a plane is available includes reading a status register of the flash memory device by coupling status request signals to the flash memory device.

10. The method of claim 7 wherein step b) occurs in a clock cycle immediately following step a).

11. The method of claim 7 wherein step c) occurs in a clock cycle immediately following step b).

12. The method of claim 7 wherein step d) occurs in a clock cycle immediately following step c).

13. A computer implemented method of increasing data throughput of a flash memory device, the flash memory device including a flash memory array, an array controller and a page buffer, the page buffer including a first plane and a second plane, the array controller controlling a programming of the flash memory array, the array controller being coupled to the page buffer, the method comprising the computer implemented steps of:

a) loading the first plane with a first block of data by sequentially coupling a first set of data signals representing the first block of data to the flash memory device;

b) commanding the array controller to program the flash memory array with the first block of data stored in the first plane by coupling command signals representing a command to program from the page buffer;

c) while the array controller is programming the flash memory array with the first block of data stored in the first plane, loading the second plane with a second block of data by sequentially coupling data signals representing the second block of data to the flash memory; and

d) commanding the array controller to program the flash memory array with the second block of data stored in the second plane by coupling command signals representing a command to program from the page buffer to the flash memory device.

14. The method of claim 13 further comprising the step of:

a) first determining whether a plane of the page buffer is available.

15. The method of claim 14 wherein the step of determining whether a plane is available includes reading a status register of the flash memory device.

16. The method of claim 13 wherein step b) occurs in a clock cycle immediately following step a).

17. The method of claim 13 wherein step c) occurs in a clock cycle immediately following step b).

18. The method of claim 13 wherein step d) occurs in a clock cycle immediately following step c).

19. The method of claim 13 wherein the first plane and the second plane of the page buffer comprises static random access memory.

20. The method of claim 13 wherein the step of loading the first plane further comprises the step of:

first commanding a sequential load of the page buffer by coupling command signals representing the sequential load of the page buffer to the flash memory device.

21. The method of claim 20 wherein commanding the sequential load of the page buffer includes the step of:

signaling a number of bytes of data to be loaded into the page buffer.

22. The method of claim 13 wherein the step of loading the second plane further comprises the step of:

first commanding a sequential load of the page buffer by coupling command signals representing the sequential load of the page buffer to the flash memory device.

23. The method of claim 22 wherein commanding the sequential load of the page buffer includes the step of:

signaling a number of bytes of data to be loaded into the page buffer.

24. The method of claim 13 wherein the steps of commanding the array controller to program the flash memory array from the page buffer include signaling a starting address within flash memory array.