Monolithic integrated structure to protect a power transistor against overvoltage

• US 5,521,414 A
• Filed: 04/28/1994
• Issued: 05/28/1996
• Est. Priority Date: 04/28/1993
• Status: Expired due to Term

• Current Assignee: Consorzio Per La Ricerca Sulla Microelecttronica Nel Mezzogiorno
• Original Assignee: SGS-Thomson Microelectronics, S.R.L. (STMicroelectronics NV)
• Inventors: Palara, Sergio
• Primary Examiner(s): LOKE, STEVEN HO YIN
• Application Number:
  US08/234,334
• Time in Patent Office: 761 Days
• Field of Search: 257/355, 257/356, 257/362, 257/328, 257/500, 257/502, 257/552, 257/603, 257/551, 257/577, 257/341
• US Class Current: 257/355
• CPC Class Codes: H01L 27/0248 for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
• CPC Class Codes: H01L 27/0255 using diodes as protective elements
• CPC Class Codes: H01L 27/0664 Vertical bipolar transistor in combination with diodes
• CPC Class Codes: H01L 29/7808 the other device being a breakdown diode, e.g. Zener diode
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A structure of an electronic device having a predetermined unidirectional conduction threshold is formed on a chip of an N-type semiconductor material and includes a plurality of isolated N-type regions. Each isolated N-type region is bounded laterally by an isolating region and at the bottom by buried P-type and N-type regions which form in combination a junction with a predetermined reverse conduction threshold and means of connecting the junctions of the various isolated regions serially together. The buried N-type region of the first junction in the series is connected to a common electrode, which also is one terminal of the device, over an internal path of the N-type material of the chip, and the buried P-type region of the last junction in the series contains an additional buried N-type region which is connected electrically to a second terminal of the device.

Claims

1. An integrated structure of an electronic device having a predetermined unidirectional conduction threshold, which structure is formed on a chip of an N-type semiconductor material and comprises:

a plurality of N-type isolated regions extending into the chip from a first surface of the chip and being each bounded laterally by a P-type isolating region, and at the bottom, by a pair of buried regions of P-type and N-type which form a p-n junction therebetween, the P-type buried region of the pair being joined to the isolating region;

first means of electric connection between opposite-type regions of said pairs of buried regions, which connect respective p-n junctions serially together;

second means of electric connection between the N-type buried region of the buried region pair forming the first p-n junction in the series and a first terminal of the device;

the isolated region of said plurality of N-type isolated regions bounded at the bottom by the buried region pair which form the last p-n junction in the series comprising an additional buried region of the N-type which forms an additional p-n junction with the respective buried region of the P-type; and

third means of electric connection between the additional buried region of the N-type and a second terminal of the device.

2. A structure according to claim 1 wherein the first terminal of the device is formed on a second surface of the chip opposite from said first surface;

and

the buried region of the P-type of the buried region pair forming the first p-n junction in the series is shaped such that the buried region of the N-type forming a p-n junction therewith is in contact with an N-type material portion of the chip outside its respective isolated region, whereby the N-type material portion included between that buried region of the N-type of the first p-n junction in the series and the first terminal of the device is a part of the second connection means.

3. A structure according to claim 2 wherein the first connection means comprise deep contact regions of the N-type each extending from the first surface of the chip to the buried region of the N-type of each of the buried region pairs, with the exception of the buried region pair which forms the first p-n junction in the series;

and

the third means of connection comprise an additional deep contact region of the N-type extending from the first surface of the chip to the additional buried region of the N-type.

4. A structure according to claim 1 wherein the first connection means comprise metallic paths extending across the first surface of the chip, said metallic paths being in ohmic contact with selected surface areas of the P-type isolation regions and with selected surface areas of N-type deep contact regions extending from the first surface of the chip to the buried region of the N-type of each of the buried region pairs, with the exception of the buried region pair which forms the first p-n junction in the series;

and

the third connection means comprise an additional metallic path in ohmic contact with a selected surface area of an additional deep contact region of the N-type extending from the first surface of the chip to the additional buried region of the N-type.

5. A protection device against overvoltages between the collector and the emitter terminals of a bipolar power transistor, integrated to a structure as claimed in claim 1 wherein said first and second terminals are the terminals of the protection device and are respectively connected to the collector terminal and the base terminal of the bipolar power transistor.

6. A protection device against overvoltages between the drain and the source terminals of a field-effect power transistor, integrated to a structure as claimed in claim 1 wherein said first and second terminals are the terminals of the protection device and are respectively connected to the drain and the gate terminals of the field-effect power transistor.

7. An integrated structure of an electronic device having a predetermined unidirectional conduction threshold formed on a chip of an N-type semiconductor material, comprising:

an isolated region of the N-type extending into the chip from a first surface of the chip and being bounded laterally by an isolating region of the P-type and at the bottom by a buried region of the P-type and by first and second buried regions of the N-type which form, together with the buried region of the P-type, first and second p-n junctions, respectively, the buried region of the P-type being joined to the isolating region;

a first electric connection between the first buried region of the N-type and a first terminal of the device; and

a second electric connection between the second buried region of the N-type and a second terminal of the device.

8. A structure according to claim 7 wherein the first terminal of the device is formed on the opposite chip surface from said first surface;

and

the buried region of the P-type is shaped such that the first buried region of the N-type is in contact with an N-type material portion of the chip outside the isolated region, whereby the portion of the N-type material included between said first buried region of the N-type and the first terminal of the device is a part of the first electric connection.

9. A structure according to claim 8 wherein the second electric connection comprises a deep contact region extending from the first surface of the chip to the second buried region of the N-type.

10. An integrated circuit structure formed on a chip having a substrate of a first conductivity type, the structure comprising:

a plurality of isolated regions of the first conductivity type, each of said isolated regions extending into said chip from a first surface of said chip, each of said isolated regions being bounded laterally by an isolating region of a second conductivity type, each of said isolated regions being bounded at a bottom of said isolated region by a pair of buried regions, said pair of buried regions having a buried region of said first conductivity type and a buried region of said second conductivity type, said pair of buried regions forming a junction therebetween, said buried region of second conductivity type being joined to said isolating region;

first electrical connection means that electrically connect said junctions in series, such that said buried regions of said first conductivity type are electrically connected to said buried regions of said second conductivity type;

second electrical connection means that electrically connect a buried region of said first conductivity type in a first junction in said series of junctions and a first terminal of said circuit structure;

an additional buried region of said first conductivity type, said additional buried region being buried in the isolated region of said first conductivity type bounded at the bottom by the buried region pair forming the last junction in said series of junctions, said additional buried region forming an additional junction with the buried region of said second conductivity type forming the last junction in said series of junctions; and

third electrical connection means between said additional buried region of said first conductivity type and a second terminal of said circuit structure.

11. The structure of claim 10 wherein said first conductivity type comprises N-type semiconductor material and said second conductivity type comprises P-type semiconductor material.

12. The structure of claim 10 wherein said first conductivity type comprises P-type semiconductor material and said second conductivity type comprises N-type semiconductor material.

13. The structure of claim 10 wherein said first and second terminals are terminals of a protection device against overvoltages between collector and emitter terminals of a bipolar power transistor, said first terminal being connected to said collector terminal of said bipolar power transistor, said second terminal being connected to a base terminal of said bipolar power transistor.

14. The structure of claim 10 wherein said first and second terminals are terminals of a protection device against overvoltages between drain and source terminals of a field-effect power transistor, said first terminal being connected to said drain terminal of said field-effect power transistor, said second terminal being connected to a gate terminal of said field-effect power transistor.