Efficient method and resulting structure for integrated circuits with flexible I/O interface and power supply voltages

• US 5,521,530 A
• Filed: 08/31/1994
• Issued: 05/28/1996
• Est. Priority Date: 08/31/1994
• Status: Expired due to Fees

• Current Assignee: Oki America, Inc. (ROHM Co., Ltd.)
• Original Assignee: Oki Semiconductor America, Inc. (ROHM Co., Ltd.)
• Inventors: Yao, Chingchi, Wang, Poucheng
• Primary Examiner(s): Hudspeth, David R.
• Application Number:
  US08/299,004
• Time in Patent Office: 636 Days
• Field of Search: 326/80-81, 326/33
• US Class Current: 326/80
• CPC Class Codes: H01L 24/06 of a plurality of bonding areas
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/12032 Schottky diode
• CPC Class Codes: H01L 2924/1305 Bipolar Junction Transistor [BJT]
• CPC Class Codes: H01L 2924/13091 Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/14 Integrated circuits
• CPC Class Codes: H03K 19/018521 of complementary type, e.g. CMOS

Abstract

A semiconductor integrated circuit receives and transmits signals at more than one set of VH/VL voltage levels. The integrated circuit includes a core region, an input pad, an output pad, peripheral circuitry, and a plurality of power supply lines each at power supply voltage levels V1, V2, V3 . . . Vm. The integrated circuit also includes input circuitry and output circuitry each of which have buffers and translators. The availability of the power lines each at power supply voltage levels V1, V2, V3 . . . Vm and translators allows for the present circuit to transmit and receive various sets of input signals and output signals, all within the same integrated circuit.

Claims

1. A semiconductor integrated circuit comprising:

a core region, an input pad, an output pad, peripheral circuitry, and a plurality of power supply lines, each one of said power supply lines being coupled to one of a plurality of power supply voltage levels V1, V2, V3 . . . Vm, one of said power supply lines being coupled to a power pad supplying any one of said plurality of power supply voltage levels;

an input circuit connected to a said plurality of said power supply lines and coupled between said core region and said input pad, said input circuit being a portion of said peripheral circuitry; and

an output circuit connected to a of said plurality of said power supply lines and coupled between said core region and said output pad, said output circuit being a portion of said peripheral circuitry;

wherein said input circuit is adapted to receive an input signal at one of a plurality of voltage signal levels from said input pad and said output circuit is adapted to transmit an output signal at one of a plurality of voltage signal levels at said output pad.

2. The circuit of claim 1 wherein said input circuit comprises a translator for receiving said input signal and translating said input signal to a desired voltage range.

3. The circuit of claim 2 wherein said input circuit further comprises a level shifter coupled to said translator, said level shifter receiving said input signal and shifting said input signal to a preselected signal level.

4. The circuit of claim 1 wherein said input circuit comprises an electrostatic discharge circuit for receiving said input signal.

5. The circuit of claim 1 wherein said output circuit comprises a translator for receiving said output signal and translating said output signal to a desired voltage range.

6. The circuit of claim 5 wherein said output circuit further comprises a pre-driver coupled to said translator.

7. The circuit of claim 1 wherein said output circuit comprises an output driver for transmitting said output signal.

8. The circuit of claim 1 wherein said core region comprises CMOS devices.

9. The circuit of claim 1 wherein said input pad and said output pad are the same pad.

10. The circuit of claim 1 wherein one of said plurality of voltage levels is at 5 volts and another of said plurality of voltage levels is at 3.3 volts.

11. An integrated circuit comprising:

a core region comprising a plurality of cells;

a plurality of circuit element groups B1, B2, B3 . . . Bn each coupled to said core region, each of said circuit element groups comprising power lines supplying a plurality of voltages V1, V2, V3 . . . Vm;

a power pad coupled to one of said power lines, said power pad supplying any one of said plurality of voltages; and

a plurality of input/output pads coupled to each of said plurality of circuit element groups, said pads comprising an input pad and an output pad;

wherein each of said circuit element groups comprising an output buffer, coupled to more than one of said power lines, to provide an output signal at said one of a plurality of signal levels to said output pad.

12. The integrated circuit of claim 11 wherein each of said circuit element groups further comprising an input buffer, coupled to more than one of said power lines, to receive a first input signal from said input pad, and provide an input signal at one of said plurality of signal levels to said core region.

13. The integrated circuit of claim 11 wherein said circuit element groups being separated by a power break cell, said power break cell isolating a portion of said power lines to at least one of said circuit element groups.

14. The integrated circuit of claim 11 wherein said output buffer comprises a translator coupled to said one of said plurality of voltages V1, V2, V3 . . . Vm.

15. The integrated circuit of claim 11 wherein said output buffer comprises a pre-driver coupled to a translator.

16. The integrated circuit of claim 15 wherein said pre-driver is coupled to one of said power lines having the same voltage level as said core region.

17. The integrated circuit of claim 11 wherein said output buffer comprises an output driver coupled to one of said power lines at one of said plurality of voltage levels.

18. The integrated circuit of claim 12 wherein said input buffer comprises a level shifter coupled to said input pad.

19. The integrated circuit of claim 12 wherein said input buffer comprises an input translator coupled to a level shifter.

20. The integrated circuit of claim 12 wherein said input buffer and said output buffer comprise CMOS devices.

21. The integrated circuit of claim 12 wherein at least one of said circuit element groups comprise power lines at a single voltage level.

22. An integrated circuit comprising:

a core region, an input pad, an output pad, peripheral circuitry, and a plurality of power supply lines;

an output circuit connected to a plurality of said power supply lines and coupled between said core region and said output pad, said output circuit being a portion of said peripheral circuitry; and

a first power pad connected to one of said plurality of power supply lines, said power pad supplying any one of a plurality of first power supply voltage levels V1, V2 . . . V_m (m>

1);

wherein said output circuit transmits an output signal with reference to one of said plurality of first power supply voltage levels.

23. The integrated circuit of claim 22 further comprising:

an input circuit connected to a plurality of said power supply lines and coupled between said core region and said input pad, said input circuit being a portion of said peripheral circuitry; and

a second power pad connected to one of said plurality of power supply lines, said second power pad supplying any one of a plurality of second power supply voltage levels V1, V2 . . . V_n (n>

1);

wherein said input circuit transmits an input signal with reference to one of said plurality of second power supply voltage levels.

24. The integrated circuit of claim 23 wherein said first pad and said second pad are the same.

25. The integrated circuit of claim 23 wherein said output pad and said input pad are the same.

26. A method of supplying power to an integrated circuit device, said method comprising:

providing a semiconductor integrated circuit, said semiconductor integrated circuit comprising a core region, an input pad, an output pad, peripheral circuitry, a plurality of power supply lines, an output circuit connected to a plurality of said power supply lines and coupled between said core region and said output pad, said output circuit being a portion of said peripheral circuitry;

providing a first power pad connected to one of said plurality of power supply lines;

supplying any one of a plurality of first power supply voltage levels V1, V2 . . . V_m (m>

1) to said first power pad;

transmitting through said output circuit an output signal with reference to one of said plurality of first power supply voltage levels.

27. The integrated circuit of claim 26 further comprising:

providing an input circuit connected to a plurality of said power supply lines and coupled between said core region and said input pad, said input circuit being a portion of said peripheral circuitry;

providing a second power pad connected to one of said plurality of power supply lines, said second power pad supplying any one of a plurality of second power supply voltage levels V1, V2 . . . V_n (n>

1); and

transmitting through said input circuit an input signal with reference to one of said plurality of second power supply voltage levels.