CMOS static memory

• US 5,521,860 A
• Filed: 12/16/1994
• Issued: 05/28/1996
• Est. Priority Date: 12/20/1993
• Status: Expired due to Fees

• Current Assignee: NEC Electronics Corporation (Renesas Electronics Corporation)
• Original Assignee: NEC Corporation
• Inventors: Ohkubo, Hiroaki
• Primary Examiner(s): Nelms, David C.
• Assistant Examiner(s): LE, VU ANH
• Application Number:
  US08/358,017
• Time in Patent Office: 529 Days
• Field of Search: 365/154, 257/903, 257/69, 257/369, 257/385, 257/351
• US Class Current: 365/154
• CPC Class Codes: H10B 10/12 comprising a MOSFET load element
• CPC Class Codes: Y10S 257/903 FET configuration adapted for use as static memory cell

Abstract

Two intracell wiring serving as the gate electrodes of driver transistors and load transistors and arranged substantially parallel to each other between two word lines substantially parallel to each other so as to be perpendicular to the word lines are arranged as the first layer. Ground wiring and a power supply wiring are arranged as the second layer on the first layer through an insulating film. Each intracell wiring serves as the gate electrodes of one driver transistor and one load transistor and is connected to the drain regions of the other driver transistor and the other load transistor. The ground wiring are connected to the source regions of the driver transistors, and the power supply wiring is connected to the source regions of the load transistors.

Claims

1. A CMOS static memory including first and second driving transistors, first and second load transistors, and first and second switching transistors respectively arranged point symmetrical in a memory cell, comprising:

first and second word lines serving as gate electrodes of said first and second switching transistors and arranged substantially parallel to each other;

said first and second driver transistors and said first and second load transistors arranged between said substantially parallel word lines on a single substrate of said memory cell;

said two load transistors, said two driver transistors, and said two word lines arranged point symmetrical in a linear fashion on a single substrate surface;

first and second intracell wiring arranged substantially parallel to each other between said two word lines so as to be perpendicular to said word lines and wherein said first and second word lines and said first and second intracell wiring are arranged on the same layer; and

ground wiring and a power supply wiring arranged on said word lines and said first and second intracell wiring through an insulating film.

2. A CMOS static memory including first and second driver transistors, first and second load transistors, and first and second switching transistors respectively arranged point symmetrical in a memory cell, comprising:

first and second word lines serving as gate electrodes of said first and second switching transistors and arranged substantially parallel to each other;

first and second intracell wiring arranged substantially parallel to each other between said two word lines so as to be perpendicular to said word lines; and

ground wiring and a power supply wiring arranged on said word lines and said first and second intracell wiring through an insulating film,

wherein said first intracell wiring serves as gate electrodes of said first driver transistor and said first load transistor and is connected to drain regions of said second driver transistor and said second load transistor, said second intracell wiring serves as gate electrodes of said second driver transistor and said second load transistor and is connected to drain regions of said first driver transistor and said first load transistor, said ground wiring are respectively connected to source regions of said first and second driver transistors, and said power supply wiring is connected to source regions of said first and second load transistors.

3. A CMOS static memory including first and second driving transistors, first and second load transistors, and first and second switching transistors respectively arranged point symmetrical in a memory cell, comprising:

first and second word lines serving as gate electrodes of said first and second switching transistors and arranged substantially parallel to each other;

said first and second driver transistors and said first and second load transistors arranged between said substantially parallel word lines on a single substrate of said memory cell;

said two load transistors, said two driver transistors, and said two word lines arranged point symmetrical in a linear fashion on a single substrate surface;

first and second intracell wiring arranged substantially parallel to each other between said two word lines so as to be perpendicular to said word lines and on the same layer as said two word lines;

ground wiring and a power supply wiring arranged on said word lines and said first and second intracell wiring through an insulating film; and

first and second data lines arranged substantially parallel to each other on said ground wiring, and said power supply wiring through an insulating film.