Time slot exchanger mechanism in a network for data communication having isochronous capability

• US 5,521,928 A
• Filed: 05/11/1995
• Issued: 05/28/1996
• Est. Priority Date: 11/02/1992
• Status: Expired due to Term

• Current Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Original Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Inventors: Edem, Brian C., Evans, Michael S., Worsley, Debra J.
• Primary Examiner(s): Chin, Wellington
• Assistant Examiner(s): Nguyen, Chau T.
• Application Number:
  US08/439,440
• Time in Patent Office: 383 Days
• Field of Search: 370/66, 370/94.3, 370/67, 370/16.1, 370/68, 370/94.2, 370/60, 370/110.1, 370/100.1, 370/105.1, 370/105.3, 370/85.15, 370/85.1, 370/95.1, 370/85.7, 370/91 , 370/85.4, 370/85.5, 370/108, 340/825.05, 375/368, 375/371
• US Class Current: 370/362
• CPC Class Codes: F02B 2075/025 two
• CPC Class Codes: H04L 12/44 Star or tree networks
• CPC Class Codes: H04L 12/6418 Hybrid transport
• CPC Class Codes: H04L 2012/644 Star
• CPC Class Codes: H04L 2012/6454 Random, e.g. Ethernet
• CPC Class Codes: H04L 2012/6459 Multiplexing, e.g. TDMA, CDMA

Abstract

An apparatus and method for transferring data between two entities in a time slot interchange fashion. The apparatus and method includes a buffer memory comprised of three sections to accommodate up to one cycle of skew between the two independently operating entities. Cycle start detection logic coupled to the two entities controls or, as implemented in the preferred embodiment, designates a physical location within the buffer memory for each of the three sections upon receipt of cycle start reference signals from the two entities.

Claims

1. Apparatus for communicating between first and second entities in a time slot interchange fashion, the apparatus comprising:

a storage memory having first, second and third memory sections;

wherein said first memory section is coupled to receive data from said first entity;

wherein said second memory section is adapted to store data received from said first entity prior to receipt of said data by said first memory section;

wherein said third memory section is coupled to said second entity and outputs to said second entity data received from said first entity at a time previous to receipt of said data stored in said second memory section;

means coupled to said first and second entities for receiving a first cycle start reference from said first entity indicating the start of a cycle of data of said first entity and a second cycle start reference from said second entity indicating the start of a cycle of data of said second entity, respectively; and

control means coupled to said means for receiving for alternately assigning first, second and third physical storage locations to said first, second and third memory sections, respectively, responsive to receipt of said first and second cycle start references.

2. The apparatus of claim 1 wherein said first, said second and said third memory sections each comprise an individual ping pong buffer.

3. The apparatus of claim 1 wherein said storage memory is comprised of a single physical memory unit.

4. The apparatus of claim 1, wherein said control means designates said third memory section responsive to said second cycle start reference and designates said first and second memory sections responsive to said first cycle start reference.

5. The apparatus of claim 1 wherein said data are isochronous.

6. The apparatus of claim 1 wherein said third memory section is adapted to output said data to said second entity in a different order than as received from said first entity.

7. The apparatus of claim 1 wherein said means for receiving is comprised of cycle start detection logic.

8. The apparatus of claim 1 wherein said control means is comprised of cycle start detection logic.

9. Apparatus for communicating between first and second stations in a data communication system over a link, said data communication system including a plurality of data sources and sinks, a first of said sources and sinks configured to receive or transmit data isochronously and a second of said sources and sinks configured to transmit data non-isochronously, the apparatus comprising:

a first receiver and a first transmitter in said first station;

said link coupling said first station with said second station;

said second station being coupled to both said first and second sources and sinks;

a second transmitter in said second station adapted to transmit data to said first receiver;

a multiplexer in said second station adapted to permit the transmission of data from both said first and second sources and sinks over said link as multiplexed data, said multiplexer providing a dedicated bandwidth for data originating from an isochronous source, including said first of said sources and sinks; and

means, coupled to said first and second stations, for exchanging said isochronous data over said link including;

a storage memory having first, second and third memory sections;

wherein said first memory section is coupled to receive data from said second station;

wherein said second memory section is adapted to store data received from said second station prior to receipt of said data by said first memory section;

wherein said third memory section is coupled to said first station for outputting data received from said second station at a time previous to receipt of said data stored in said second memory section, to said first station;

means coupled to said second and first stations for receiving a first cycle start reference from said second station indicating the start of a cycle of data of said first station and a second cycle start reference from said first station indicating the start of a cycle of data of said second station, respectively; and

control means coupled to said means for receiving for alternately assigning first, second, and third physical storage locations to said first, second and third memory sections responsive to receipt of said first and second cycle start references.

10. The apparatus of claim 9 wherein said third memory section is adapted to output said data to said first station in a different order than as received from said second station.

11. The apparatus of claim 9 wherein said means for receiving is comprised of cycle start detection logic.

12. The apparatus of claim 9 wherein said control means is comprised of cycle start detection logic.

13. In a data communications system, a method for exchanging data between first and second entities in a time slot interchange fashion comprising the steps of:

receiving data from said first entity and placing said data in a first portion of memory;

storing data received from said first entity prior to receipt of said data by said first portion of memory, in a second portion of memory;

outputting to said second entity, from a third portion of memory, data received by said third portion of memory from said first entity at a time earlier than said data is received by said second portion of memory;

alternately designating a first one of three physical memory locations for said first portion of memory and a second one of said three physical memory locations for said second portion of memory upon receipt of a first cycle frame reference from said first entity; and

alternately designating a third one of said three physical memory locations for said third portion of memory upon receipt of a second cycle frame reference from said second entity such that said three physical memory locations are alternately designated for said first, second and third portions of memory.

14. The method of claim 13 wherein the designating steps further comprise the steps of designating individual ones of three ping pong buffers as said first, second and third memory portions, respectively.

15. The method of claim 13 wherein said designating steps comprise the steps of designating first, second and third physical regions of a common memory, respectively.

16. The method of claim 13 wherein said data is isochronous.

17. The method of claim 13 wherein said third portion of memory is adapted to output said data to said second entity in a different order than as received from said first entity.

18. Apparatus for exchanging data between first and second entities in a time slot interchange fashion, the apparatus comprising:

a buffer memory coupled to said first and second entities comprised of first, second and third physical memory sections;

means coupled to said first and second entities for receiving a cycle start reference from said first entity indicating the start of a cycle of data from said first entity and a cycle start reference from said second entity indicating the start of a cycle of data from said second entity; and

means coupled to said means for receiving for designating the first, second and third physical memory sections to alternately;

(1) input data from said first entity responsive to receipt by said means for receiving of a cycle start reference from said first entity,

(2) hold data received from said first entity responsive to a preceding cycle start reference from said first entity upon receipt by said means for receiving of said cycle start reference from said first entity, and

(3) output data received during a further preceding cycle start reference from said first entity to said second entity upon receipt by said means for receiving of a first cycle start reference from said second entity.

19. The apparatus of claim 18 wherein said data is isochronous.

20. The apparatus of claim 18 wherein said third physical memory section is adapted to output said data to said second entity in a different order than as received from said first entity.

21. The apparatus of claim 18 wherein said means for receiving is comprised of cycle start detection logic.

22. The apparatus of claim 18 wherein said means for designating is comprised of cycle start detection logic.

23. The apparatus of claim 18 wherein

(1) said means for designating, upon receipt of said cycle start reference from said first entity,

(a) designates said first physical memory section to input data from a cycle of data from said first entity corresponding to said cycle start reference from said first entity and

(b) designates said second physical memory section to hold data which was inputted to said second physical memory section from a cycle of data from said first entity corresponding to a preceding cycle start reference from said first entity, and

(2) said means for designating, upon receipt of said cycle start reference signal from said second entity, designates said third physical memory section to output data from a further preceding cycle of data from said first entity.

24. In a data communications system, a method for exchanging data between first and second entities in a time slot interchange fashion comprising the steps of:

inputting first data from said first entity into a first memory section upon receiving a first cycle start reference from said first entity indicating the start of a first cycle of data from said first entity;

outputting said first data to said second entity from said first memory section upon receiving a first cycle start reference from said second entity indicating a start of a new cycle of data from said second entity;

inputting second data from said first entity into a second memory section upon receiving a second cycle start reference from said first entity;

outputting said second data to said second entity from said second memory section upon receiving a second cycle start reference from said second entity indicating the start of a second cycle of data from said second entity;

inputting third data from said first entity into a third memory section upon receiving a third cycle start reference from said first entity; and

outputting said third data from said second entity from said third memory section upon receiving a third cycle start reference from said second entity indicating the start of a third cycle of data from said second entity.

25. The method of claim 24 wherein said first, second and third data are isochronous.

26. The method of claim 24 herein said first data is adapted to be output from said memory section in a different order than as input to said first memory section.