Apparatus for performing frequency conversion in a communication system

• US 5,521,938 A
• Filed: 07/01/1994
• Issued: 05/28/1996
• Est. Priority Date: 07/01/1994
• Status: Expired due to Term

• Current Assignee: Google Technology Holdings LLC (Alphabet Inc.)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Love, Robert T., Stewart, Kenneth A.
• Primary Examiner(s): Gregory, Bernarr E.
• Application Number:
  US08/276,073
• Time in Patent Office: 697 Days
• Field of Search: 328/15, 328/156, 328/158, 328/159, 328/165, 328/166, 329/301, 329/303, 329/305, 329/310, 307/424, 307/529, 307/260, 307/261, 307/269, 307/271, 307/272.1, 375/200-210, 375/1, 380/34
• US Class Current: 375/146
• CPC Class Codes: H03D 2200/005 Analog to digital conversion
• CPC Class Codes: H03D 2200/0056 including a digital decimation filter
• CPC Class Codes: H03D 2200/006 Signal sampling
• CPC Class Codes: H03D 2200/0068 by computation
• CPC Class Codes: H03D 2200/0072 by complex multiplication
• CPC Class Codes: H03D 2200/008 Hilbert type transformation
• CPC Class Codes: H03D 3/007 by converting the oscillations into two quadrature related signals H03D3/245 takes precedence
• CPC Class Codes: H04B 1/0003 Software-defined radio [SDR] systems, i.e. systems wherein components typically implemented in hardware, e.g. filters or modulators/demodulators, are implented using software, e.g. by involving an AD or DA conversion stage such that at least part of the signal processing is performed in the digital domain digital baseband systems H04L25/00; digital modulation/demodulation H04L27/00; CDMA H04B1/707; TDMA H04B7/2643; image transmission H04N5/00
• CPC Class Codes: H04B 1/0021 Decimation, i.e. data rate reduction techniques H04B1/0025 takes precedence
• CPC Class Codes: H04B 1/0032 with analogue quadrature frequency conversion to and from the baseband quadrature modulators and demodulators per se H03D3/007, H03C3/40
• CPC Class Codes: H04B 1/0046 Decimation, i.e. data rate reduction techniques
• CPC Class Codes: H04B 1/26 for superheterodyne receivers multiple frequency-changing H03D7/16

Abstract

An efficient apparatus for performing frequency conversion from a final IF frequency to a baseband frequency is described. A counter (401) generates two logical signals G1 (402) and G2 (403) which are passed to an exclusive-OR gate (404) and a multiplexer (406). When a control signal (411) is deasserted, multiplexer (406) passes signal G1 to I1 and signal G2 to I2; when control signal (411) is asserted, multiplexer (406) passes binary signal G1 to I2 (410) and signal G2 to I1 (407). Similarly, multiplexer (405) swaps its input real and imaginary samples when the output of exclusive-OR gate (404) is asserted; otherwise, it performs no operation on its input samples. Signals I1 (407) and I2 (410) are used to control arithmetic inverters (408) and (409) respectively. When the controlling signal for either inverter is asserted, the inverter performs arithmetic inversion, otherwise it performs no operation.

Claims

1. An apparatus for performing frequency conversion in a communication system, the apparatus comprising:

a counter having a clock signal as input and a plurality of signals as output;

a switch having as input and output in-phase and quadrature components of a signal at a first frequency and having as input a control signal for interchanging as output the in-phase and quadrature components of the signal at the first frequency;

at least one inverter, having as input the in-phase and quadrature components of the signal output of the switch and one of the plurality of signals output from the counter and having as output the in-phase and quadrature components of the signal at a second frequency; and

a logic gate, having as input the plurality of signals output from the counter and as output the control signal based on a combination of the plurality of signals output from the counter.

2. The apparatus of claim 1 wherein the first frequency or second frequency is either a baseband frequency or a passband frequency.

3. The apparatus of claim 1 wherein the counter further comprises a Gray counter.

4. The apparatus of claim 1 wherein the logic gate further comprises an exclusive-OR (XOR) logic gate.

5. The apparatus of claim 1 wherein the apparatus is implemented in either a direct sequence spread spectrum (DS-SS) transmitter or receiver implementing a Hilbert filter configuration.

6. The apparatus of claim 1 wherein the output of the inverter further comprises the in-phase and quadrature components of the signal at a second frequency being output from a plurality of inverters.

7. An apparatus for despreading a spread spectrum signal, the apparatus comprising:

signal receiving means, for receiving the spread spectrum signal;

a digitizer coupled to the signal receiving means;

a Hilbert filter configuration, coupled to the digitizer;

a counter having a clock signal as input and a plurality of signals as output;

plurality of pseudo-random noise generators;

a decoder coupled to the pseudorandom noise generators and outputting control information;

a multiplexer having input from the Hilbert filter configuration and outputting a signal sample arguments; and

first and second accumulators, having as input the signal sample arguments, for accumulating the signal sample arguments based on the control information.

8. The apparatus of claim 7 wherein the first and second accumulators accumulate by either adding or subtracting the signal sample arguments from an accumulated value.

9. The apparatus of claim 7 wherein the apparatus is implemented in a direct sequence spread spectrum (DS-SS) receiver.

10. An apparatus for spreading a signal to generate a spread spectrum signal, the apparatus comprising;

a counter having a clock signal as input and a plurality of signals as output;

a plurality of pseudo-random sequence generators;

a decoder for generating multi-phase spread transmit signals based on input from the plurality of pseudo-random sequences generators and a combination of the plurality of signals from the counter; and

a converter for converting the generated multi-phase spread transmit signals into a form for transmission.

11. The apparatus of claim 10 wherein the multi-phase spread transmit signals further comprises either biphase spread transmit signals or quadriphase spread transmit signals.

12. The apparatus of claim 10 wherein the converter further comprises a 1-bit D/A converter.