Phase detection reset in phase locked loops used for direct VCO modulation

• US 5,521,947 A
• Filed: 05/09/1994
• Issued: 05/28/1996
• Est. Priority Date: 03/10/1993
• Status: Expired due to Term

• Current Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Original Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Inventors: Madsen, Benny
• Primary Examiner(s): Chin, Stephen
• Assistant Examiner(s): Bocure, Tesfaldet
• Application Number:
  US08/239,451
• Time in Patent Office: 750 Days
• Field of Search: 375/375, 375/376, 327/143, 327/155, 327/156, 327/144, 327/146, 327/147
• US Class Current: 375/375
• CPC Class Codes: H03B 2201/0208 the means being an element with a variable capacitance, e.g. capacitance diode
• CPC Class Codes: H03B 5/18 with frequency-determining element comprising distributed inductance and capacitance
• CPC Class Codes: H03C 3/095 applying frequency modulation to the loop in front of the voltage controlled oscillator
• CPC Class Codes: H03L 2207/06 Phase locked loops with a controlled oscillator having at least two frequency control terminals
• CPC Class Codes: H03L 7/183 a time difference being used for locking the loop, the counter counting between fixed numbers or the frequency divider dividing by a fixed number H03L7/1806 takes precedence
• CPC Class Codes: H04B 1/408 the transmitter oscillator frequency being identical to the receiver local oscillator frequency
• CPC Class Codes: H04B 1/56 with provision for simultaneous communication in two directions
• CPC Class Codes: H04L 27/10 Frequency-modulated carrier systems, i.e. using frequency-shift keying H04L27/32 takes precedence
• CPC Class Codes: H04L 27/12 Modulator circuits; Transmitter circuits
• CPC Class Codes: H04L 27/148 using filters, including PLL-type filters
• CPC Class Codes: H04L 27/152 using controlled oscillators, e.g. PLL arrangements
• CPC Class Codes: H04L 5/143 for modulated signals H04L5/1469 takes precedence
• CPC Class Codes: H04L 5/1492 with time compression, e.g. operating according to the ping-pong technique

Abstract

A phase-lock loop (PLL) includes a switch for opening the loop (e.g. for direct modulation of its voltage-controlled oscillator (VCO) during transmission of an intermittent signal such as data bursts) and has a phase comparator which can be selectively initialized (e.g. by setting to a programmed value or resetting to zero or terminal count value the reference and/or feedback signal frequency dividers) so that upon "re-closing" of the loop the PLL will achieve phase-lock within a predetermined amount of time. When the loop is opened, the VCO'"'"'s dc ("phase-lock") control voltage can be maintained so as to help ensure that phase-lock will be achieved within the desired amount of time.

Claims

1. A phase-lock loop (PLL) in which the loop is selectively opened and then re-closed to re-achieve phase-lock with a reference signal within a selectively predetermined phase-settling time interval, comprising:

frequency-tunable oscillator means for selectively receiving a PLL tuning signal and in accordance therewith providing a closed-loop oscillator signal, and for providing an open-loop oscillator signal which includes a plurality of open-loop carrier frequencies when said PLL tuning signal is not being received, wherein initially upon said receiving of said PLL tuning signal said closed-loop oscillator signal includes a plurality of phase-unlocked closed-loop carrier frequencies and phases, and after said phase-settling time interval includes a phase-locked closed-loop carrier frequency and phase;

signal comparator means, coupled to said frequency-tunable oscillator means, for receiving said closed-loop oscillator signal and a reference oscillator signal which includes a reference carrier frequency and phase, and for comparing said closed-loop oscillator signal with said reference oscillator signal and in accordance therewith providing to said frequency-tunable oscillator means a closed-loop tuning signal as said PLL tuning signal, and further for receiving a comparator initialization signal in accordance with which said phase-settling time interval can be selectively predetermined, wherein said signal comparator means comprises signal disabler means for receiving a loop command signal and in accordance therewith enabling and disabling said providing of said PLL tuning signal to said frequency-tunable oscillator means, and wherein said signal disabler means comprises carrier holder means for receiving said loop command signal and in accordance therewith providing during a hold time interval a tuning hold signal substantially equal to said PLL tuning signal as provided immediately prior to said receiving of said loop command signal, wherein said phase-locked closed-loop carrier phase of said closed-loop oscillator signal is phase-locked to said reference oscillator signal, and wherein during said hold time interval each one of said plurality of open-loop carrier frequencies is approximately equal to said phase-locked closed-loop carrier frequency.

2. A PLL as recited in claim 1, wherein said carrier holder means comprises an input signal port for receiving a power down signal in accordance with which said signal comparator means is turned off.

3. A PLL as recited in claim 1, wherein said carrier holder means comprises a switch.

4. A PLL as recited in claim 1, wherein said signal comparator means further comprises a phase comparator for comparing said phase-locked and phase-unlocked closed-loop carrier phases of said closed-loop oscillator signal with said reference carrier phase of said reference oscillator signal, and wherein said PLL tuning signal comprises a phase difference signal.

5. A PLL as recited in claim 4, wherein said signal comparator means still further comprises reference divider means, coupled to said phase comparator for receiving and frequency-dividing said reference oscillator signal in accordance with a reference divisor.

6. A PLL as recited in claim 5, wherein said comparator initialization signal comprises a reference divider preset signal for presetting said reference divisor.

7. A PLL as recited in claim 4, wherein said signal comparator means still further comprises feedback divider means, coupled to said phase comparator, for receiving and frequency-dividing said closed-loop oscillator signal in accordance with a feedback divisor.

8. A PLL as recited in claim 7, wherein said comparator initialization signal comprises a feedback divider preset signal for presetting said feedback divisor.

9. A phase-lock loop (PLL) in which the loop is selectively opened and then re-closed to re-achieve phase-lock with a reference signal within a selectively predetermined phase-settling time interval, comprising:

a frequency-tunable oscillator which selectively receives a PLL tuning signal and in accordance therewith provides a closed-loop oscillator signal, and which provides an open-loop oscillator signal including a plurality of open-loop carrier frequencies when said PLL tuning signal is not being received, wherein initially upon said receiving of said PLL tuning signal said closed-loop oscillator signal includes a plurality of phase-unlocked closed-loop carrier frequencies and phases, and after said phase-settling time interval includes a phase-locked closed-loop carrier frequency and phase;

a signal comparator, coupled to said frequency-tunable oscillator, which receives said closed-loop oscillator signal and a reference oscillator signal including a reference carrier frequency and phase, and which compares said closed-loop oscillator signal with said reference oscillator signal and in accordance therewith provides to said frequency-tunable oscillator a closed-loop tuning signal as said PLL tuning signal, and which further receives a comparator initialization signal in accordance with which said phase-settling time interval can be selectively predetermined, wherein said signal comparator comprises a signal disabler which receives a loop command signal and in accordance therewith enables and disables said providing of said PLL tuning signal to said frequency-tunable oscillator, and wherein said signal disabler comprises a carrier holder which receives said loop command signal and in accordance therewith provides during a hold time interval a tuning hold signal substantially equal to said PLL tuning signal as provided immediately prior to said receiving of said loop command signal, wherein said phase-locked closed-loop carrier phase of said closed-loop oscillator signal is phase-locked to said reference oscillator signal, and wherein during said hold time interval each one of said plurality of open-loop carrier frequencies is approximately equal to said phase-locked closed-loop carrier frequency.

10. A PLL as recited in claim 9, wherein said carrier holder comprises an input signal port which receives a power down signal in accordance with which said signal comparator is turned off.

11. A PLL as recited in claim 9, wherein said carrier holder comprises a switch.

12. A PLL as recited in claim 9, wherein said signal comparator further comprises a phase comparator which compares said phase-locked and phase-unlocked closed-loop carrier phases of said closed-loop oscillator signal with said reference carrier phase of said reference oscillator signal, and wherein said PLL tuning signal comprises a phase difference signal.

13. A PLL as recited in claim 12, wherein said signal comparator still further comprises a reference divider, coupled to said phase comparator, which receives and frequency-divides said reference oscillator signal in accordance with a reference divisor.

14. A PLL as recited in claim 13, wherein said comparator initialization signal comprises a reference divider preset signal which presets said reference divisor.

15. A PLL as recited in claim 12, wherein said signal comparator still further comprises a feedback divider, coupled to said phase comparator, which receives and frequency-divides said closed-loop oscillator signal in accordance with a feedback divisor.

16. A PLL as recited in claim 15, wherein said comparator initialization signal comprises a feedback divider preset signal which presets said feedback divisor.

17. A method of operating a phase-lock loop (PLL) in which the loop is selectively opened and then re-closed to re-achieve phase-lock with a reference signal within a selectively predetermined phase-settling time interval, comprising the steps of:

selectively receiving a PLL tuning signal and in accordance therewith generating a closed-loop oscillator signal, wherein initially upon said receiving of said PLL tuning signal said closed-loop oscillator signal includes a plurality of phase-unlocked closed-loop carrier frequencies and phases, and after said phase-settling time interval includes a phase-locked closed-loop carrier frequency and phase;

generating an open-loop oscillator signal which includes a plurality of open-loop carrier frequencies when said PLL tuning signal is not being received;

receiving a loop command signal and in accordance therewith enabling and disabling said receiving of said PLL tuning signal by receiving said loop command signal and in accordance therewith providing during a hold time interval a tuning hold signal substantially equal to said PLL tuning signal as provided immediately prior to said receiving of said loop command signal, wherein said phase-locked closed-loop carrier phase of said closed-loop oscillator signal is phase-locked to said reference oscillator signal, and wherein during said hold time interval each one of said plurality of open-loop carrier frequencies is approximately equal to said phase-locked closed-loop carrier frequency;

receiving a reference oscillator signal which includes a reference carrier frequency and phase;

comparing said closed-loop oscillator signal with said reference oscillator signal and in accordance therewith generating a closed-loop tuning signal as said PLL tuning signal; and

receiving an initialization signal and in accordance therewith preselecting said phase-settling time interval.

18. A PLL operation method as recited in claim 17, wherein said step of receiving said loop command signal and in accordance therewith providing during a hold time interval a tuning hold signal substantially equal to said PLL tuning signal as provided immediately prior to said receiving of said loop command signal comprises receiving a power down signal and in accordance therewith omitting said step of comparing said closed-loop oscillator signal with said reference oscillator signal and in accordance therewith generating a closed-loop tuning signal as said PLL tuning signal.

19. A PLL operation method as recited in claim 17, wherein said step of receiving said loop command signal and in accordance therewith providing during a hold time interval a tuning hold signal substantially equal to said PLL tuning signal as provided immediately prior to said receiving of said loop command signal comprises receiving said loop command signal and in accordance therewith switching said PLL tuning signal.

20. A PLL operation method as recited in claim 17, wherein said step of comparing said closed-loop oscillator signal with said reference oscillator signal and in accordance therewith generating a closed-loop tuning signal as said PLL tuning signal comprises comparing said phase-locked and phase-unlocked closed-loop carrier phases of said closed-loop oscillator signal with said reference carrier phase of said reference oscillator signal and in accordance therewith generating a phase difference signal as said PLL tuning signal.

21. A PLL operation method as recited in claim 20, wherein said step of comparing said closed-loop oscillator signal with said reference oscillator signal and in accordance therewith generating a closed-loop tuning signal as said PLL tuning signal further comprises frequency-dividing said reference oscillator signal in accordance with a reference divisor.

22. A PLL operation method as recited in claim 21, wherein said step of receiving an initialization signal and in accordance therewith preselecting said phase-settling time interval comprises receiving a reference divider preset signal and in accordance therewith presetting said reference divisor.

23. A PLL operation method as recited in claim 20, wherein said step of comparing said closed-loop oscillator signal with said reference oscillator signal and in accordance therewith generating a closed-loop tuning signal as said PLL tuning signal further comprises frequency-dividing said closed-loop oscillator signal in accordance with a feedback divisor.

24. A PLL operation method as recited in claim 23, wherein said step of receiving an initialization signal and in accordance therewith preselecting said phase-settling time interval comprises receiving a feedback divider preset signal and in accordance therewith presetting said feedback divisor.