Arithmetic engine with dual multiplier accumulator devices
First Claim
1. An arithmetic engine comprising:
- a first dual multiplier accumulator (MAC) for receiving input data at a first dual MAC first input and for producing first dual MAC output data at a first dual MAC output, wherein the first dual MAC comprises;
a dual multiplier for receiving a plurality of sources and for producing first and second parallel multiplier outputs, the dual multiplier including a multiplier cross point switch for receiving the plurality of sources and for producing selected sources at a plurality of multiplier cross point switch outputs, wherein the dual multiplier comprises;
a plurality of multiplier registers coupled to the multiplier cross point switch outputs, the plurality of multiplier registers for storing the selected sources as multiplier register values;
a register selector coupled to the plurality of multiplier registers, the register selector for choosing selected multiplier operands from the multiplier register values; and
first and second parallel multipliers coupled to the register selector, the first and the second parallel multipliers for receiving pairs of selected multiplier operands and multiplying the pairs of selected multiplier operands to produce the first and the second parallel multiplier outputs, respectively;
an accumulator coupled to the dual multiplier, the accumulator for receiving the first and second parallel multiplier outputs, selecting particular first and second parallel multiplier outputs in a condition code determiner, and for producing the first dual MAC output data therefrom, the accumulator comprising;
a plurality of adder registers for storing the first and the second parallel multiplier outputs and a plurality of accumulator registers for storing a first and a second accumulator output;
an accumulator cross point switch coupled to the plurality of adder registers and the plurality of accumulator registers, the accumulator cross point switch for producing selected accumulator register and adder register values from the first and the second parallel multiplier outputs and the first and the second accumulator outputs;
first and second parallel MAC adders coupled to the accumulator cross point switch, the first and the second parallel MAC adders for receiving pairs of selected accumulator register and adder register values and adding the pairs of selected accumulator register and adder register values to produce the first and the second accumulator adder outputs; and
a MAC output selector coupled to the first and to the second parallel MAC adders and to the first and to the second parallel multipliers, the MAC output selector for receiving the first and the second accumulator outputs and the first and the second parallel multiplier outputs and for producing the first dual MAC output data; and
a first dual MAC second input;
a second dual MAC coupled in parallel to the first dual MAC, the second dual MAC for receiving the input data at a second dual MAC first input and for producing second dual MAC output data at a second dual MAC output, wherein the second dual MAC comprises a second dual MAC second input; and
an adder array coupled to both the first dual MAC and to the second dual MAC, the adder array for receiving the input data, the first dual MAC output data, and the second dual MAC output data and for producing arithmetic engine output data at an adder array output, wherein the first dual MAC second input is coupled to the adder array output, the first dual MAC output is coupled to the adder array output, the second dual MAC second input is coupled to the adder array output, and the second dual MAC output is coupled to the adder array output.
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Abstract
An arithmetic engine includes a first dual multiplier accumulator (MAC) for receiving input data and for producing first dual MAC output data. A second dual MAC is coupled in parallel to the first dual MAC. The second dual MAC receives the input data and produces second dual MAC output data. An adder array is coupled to both the first dual MAC and to the second dual MAC. The adder array receives the input data, the first dual MAC output data, and the second dual MAC output data and produces arithmetic engine output data. Each dual MAC comprises a multiplier cross point switch, multiplier registers, a register selector, and parallel multipliers. Each adder array comprises a cross point switch, adder registers, a register selector, adder, and condition code determiner.
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Citations
12 Claims
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1. An arithmetic engine comprising:
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a first dual multiplier accumulator (MAC) for receiving input data at a first dual MAC first input and for producing first dual MAC output data at a first dual MAC output, wherein the first dual MAC comprises; a dual multiplier for receiving a plurality of sources and for producing first and second parallel multiplier outputs, the dual multiplier including a multiplier cross point switch for receiving the plurality of sources and for producing selected sources at a plurality of multiplier cross point switch outputs, wherein the dual multiplier comprises; a plurality of multiplier registers coupled to the multiplier cross point switch outputs, the plurality of multiplier registers for storing the selected sources as multiplier register values; a register selector coupled to the plurality of multiplier registers, the register selector for choosing selected multiplier operands from the multiplier register values; and first and second parallel multipliers coupled to the register selector, the first and the second parallel multipliers for receiving pairs of selected multiplier operands and multiplying the pairs of selected multiplier operands to produce the first and the second parallel multiplier outputs, respectively; an accumulator coupled to the dual multiplier, the accumulator for receiving the first and second parallel multiplier outputs, selecting particular first and second parallel multiplier outputs in a condition code determiner, and for producing the first dual MAC output data therefrom, the accumulator comprising; a plurality of adder registers for storing the first and the second parallel multiplier outputs and a plurality of accumulator registers for storing a first and a second accumulator output; an accumulator cross point switch coupled to the plurality of adder registers and the plurality of accumulator registers, the accumulator cross point switch for producing selected accumulator register and adder register values from the first and the second parallel multiplier outputs and the first and the second accumulator outputs; first and second parallel MAC adders coupled to the accumulator cross point switch, the first and the second parallel MAC adders for receiving pairs of selected accumulator register and adder register values and adding the pairs of selected accumulator register and adder register values to produce the first and the second accumulator adder outputs; and a MAC output selector coupled to the first and to the second parallel MAC adders and to the first and to the second parallel multipliers, the MAC output selector for receiving the first and the second accumulator outputs and the first and the second parallel multiplier outputs and for producing the first dual MAC output data; and a first dual MAC second input; a second dual MAC coupled in parallel to the first dual MAC, the second dual MAC for receiving the input data at a second dual MAC first input and for producing second dual MAC output data at a second dual MAC output, wherein the second dual MAC comprises a second dual MAC second input; and an adder array coupled to both the first dual MAC and to the second dual MAC, the adder array for receiving the input data, the first dual MAC output data, and the second dual MAC output data and for producing arithmetic engine output data at an adder array output, wherein the first dual MAC second input is coupled to the adder array output, the first dual MAC output is coupled to the adder array output, the second dual MAC second input is coupled to the adder array output, and the second dual MAC output is coupled to the adder array output. - View Dependent Claims (2, 3, 4, 5, 6)
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7. A complex arithmetic processor including an arithmetic engine comprising:
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a first dual multiplier accumulator (MAC) for receiving input data at a first dual MAC first input and for producing first dual MAC output data at a first dual MAC output, wherein the first dual MAC comprises; a dual multiplier for receiving a plurality of sources and for producing first and second parallel multiplier outputs, the dual multiplier including a multiplier cross point switch for receiving the plurality of sources and for producing selected sources at a plurality of multiplier cross point switch outputs, wherein the dual multiplier comprises; a plurality of multiplier registers coupled to the multiplier cross point switch outputs, the plurality of multiplier registers for storing the selected sources as multiplier register values; a register selector coupled to the plurality of multiplier registers, the register selector for choosing selected multiplier operands from the multiplier register values; and first and second parallel multipliers coupled to the register selector, the first and the second parallel multipliers for receiving pairs of selected multiplier operands and multiplying the pairs of selected multiplier operands to produce the first and the second parallel multiplier outputs, respectively; an accumulator coupled to the dual multiplier, the accumulator for receiving the first and second parallel multiplier outputs, selecting particular first and second parallel multiplier outputs in a condition code determiner, and for producing the first dual MAC output data therefrom, wherein the accumulator comprises; a plurality of adder registers for storing the first and the second parallel multiplier outputs and a plurality of accumulator registers for storing a first and a second accumulator output; an accumulator cross point switch coupled to the plurality of adder registers and the plurality of accumulator registers, the accumulator cross point switch for producing selected accumulator register and adder register values from the first and the second parallel multiplier outputs and the first and the second accumulator outputs; first and second parallel MAC adders coupled to the accumulator cross point switch, the first and the second parallel MAC adders for receiving pairs of selected accumulator register and adder register values and adding the pairs of selected accumulator register and adder register values to produce the first and the second accumulator adder outputs; and a MAC output selector coupled to the first and to the second parallel MAC adders and to the first and to the second parallel multipliers, the MAC output selector for receiving the first and the second accumulator outputs and the first and the second parallel multiplier outputs and for producing the first dual MAC output data; a first dual MAC second input; a second dual MAC coupled in parallel to the first dual MAC, the second dual MAC for receiving the input data at a second dual MAC first input and for producing second dual MAC output data at a second dual MAC output, wherein the second dual MAC comprises a second dual MAC second input; and an adder array coupled to both the first dual MAC and to the second dual MAC, the adder array for receiving the input data, the first dual MAC output data, and the second dual MAC output data and for producing arithmetic engine output data at an adder array output, wherein the first dual MAC second input is coupled to the adder array output, the first dual MAC output is coupled to the adder array output, the second dual MAC second input is coupled to the adder array output, and the second dual MAC output is coupled to the adder array output. - View Dependent Claims (8, 9, 10, 11, 12)
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Specification