Method and apparatus for improving the resolution of pulse position modulated communications between an implantable medical device and an external medical device

• US 5,522,866 A
• Filed: 11/01/1994
• Issued: 06/04/1996
• Est. Priority Date: 11/01/1994
• Status: Expired due to Term

• Current Assignee: Intermedics Incorporated
• Original Assignee: Intermedics Incorporated
• Inventors: Fernald, Kenneth W.
• Primary Examiner(s): Kamm, William E.
• Application Number:
  US08/333,163
• Time in Patent Office: 581 Days
• Field of Search: 607/31, 607/32, 607/60
• US Class Current: 607/60
• CPC Class Codes: A61N 1/3727 characterised by the modulation technique
• CPC Class Codes: G01R 25/005 Circuits for comparing several input signals and for indicating the result of this comparison, e.g. equal, different, greater, smaller, or for passing one of the input signals as output signal
• CPC Class Codes: H04L 7/0331 with a digital phase-locked loop [PLL] processing binary samples, e.g. add/subtract logic for correction of receiver clock H04L7/0337 takes precedence
• CPC Class Codes: Y10S 128/903 Radio telemetry

Abstract

A method and apparatus is disclosed for use in an implantable device that communicates with an external device through pulse position modulation. A timing generator is provided as part of said implantable device that determines the phase uncertainty between an external signal and an internal cock signal. The phase uncertainty then is added to the preset delay period to more precisely control the position of the response. The phase uncertainty is measured by a dual slope circuit that varies a state variable (which can be a digital timer, a capacitor voltage, or the like) at a fixed rate with either a positive or negative slope. When the external signal is detected, the state variable is reset and then decreased at a fixed rate until the next positive edge of the clock signal. The state variable then is increased at the same rate until the subsequent positive clock edge. The resulting variable value is proportional to the phase uncertainty. When the delay timer reaches zero, the state variable is again decreased at the same fixed rate until the initial value is reached, at which the output response is generated.

Claims

1. A method for improving the resolution of a pulse position modulated signal, said pulse position modulated signal providing information from an implantable medical device to an external medical device, said implantable medical device including an internal clock which generates an internal clock signal, and said external medical device generating an external signal to said implantable medical device, comprising the steps of:

measuring phase difference between the external signal and the internal clock signal;

loading a preset period into a counter to define the position of the pulse in the pulse position modulated signal;

counting the period for the preset response;

storing the phase difference;

completing the count of said preset period; and

adding an additional delay period equal to the measured phase difference.

2. A timing generator for an implantable medical device, said timing generator producing a pulse in a pulse position modulated signal, wherein the position of said pulse is determined relative to an externally generated signal from an external medical device, comprising:

a delay timer which receives at a first input terminal a signal indicative of a preset delay period, and which receives at a second input terminal a clock signal, said delay timer functioning to count for a period defined by the preset delay period, at a rate determined by the clock signal, and said delay timer providing an output signal indicative of the count of the delay timer;

a phase timer capable of counting up and down at a constant rate, said phase timer including a first input terminal for receiving a fast clock signal, a second input terminal for receiving a signal indicating the direction in which said phase timer should count, and an output terminal for providing an output signal indicative of the phase timer count;

logic circuitry coupled to said phase timer to provide a signal to said phase timer indicating the direction in which said phase timer counts;

an oscillator providing the fast clock signal to said phase timer to indicate the rate at which said phase timer counts; and

an output gate receiving the output signal from said delay timer and from said phase timer, said output gate providing the pulse in the pulse position modulated signal.

3. A timing generator as in claim 2, wherein said delay timer receives said preset delay period when said external signal is received at said implantable medical device.

4. A timing generator as in claim 2, wherein said logic circuitry includes a first and second flip-flop, with said first flip-flop producing an output signal which is received as an input by said second flip-flop, and wherein said first and second flip-flop are clocked by said internal clock signal.

5. A timing generator as in claim 4, wherein the count of said phase timer indicates the phase difference between the external signal and said internal clock signal.

6. A timing generator as in claim 4, wherein the second flip-flop produces an output signal which is provided as an input to said oscillator to turn on said oscillator.

7. A timing generator as in claim 4, wherein the output of said first flip-flop couples to the second terminal of said phase timer to indicate the direction in which said phase timer counts.

8. A timing generator for an implantable medical device, said timing generator producing a pulse for a pulse position modulated signal, wherein the position, of the pulse in the pulse position modulated signal is determined relative to an external signal generated by an external medical device, said timing generator comprising:

a delay timer which receives a signal indicative of a preset delay period, and which also receives an internal clock signal, said delay timer functioning to count for a period defined by the preset delay period, at a rate defined by the internal clock signal, and providing an output signal indicative of the count of said delay timer;

a capacitor for storing a voltage;

a first current source selectively coupled to said capacitor for increasing the voltage on said capacitor at a constant rate;

a second current source selectively coupled to said capacitor for decreasing the voltage of said capacitor at a constant rate;

logic circuitry coupled to said delay timer, said logic circuitry selectively coupling one of said current sources to said capacitor;

a voltage source providing a reference voltage; and

a comparator for comparing the voltage on said capacitor with the reference voltage for determining a period for phase difference between the internal clock signal and said external signal.

9. A timing generator as in claim 8, wherein the capacitor has a first terminal and a second terminal, and the first current source selectively connects to said capacitor causing current to flow from the first terminal of the capacitor to the second terminal of the capacitor, and the second current source selectively connects to said capacitor causing current to flow from the second terminal of the capacitor to the first terminal of the capacitor.