Mis semiconductor device and method of fabricating the same

• US 5,523,257 A
• Filed: 01/18/1994
• Issued: 06/04/1996
• Est. Priority Date: 01/18/1993
• Status: Expired due to Term

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Takemura, Yasuhika, Yamazaki, Shunpei
• Primary Examiner(s): Thomas, Tom
• Assistant Examiner(s): Picardat, Kevin M.
• Application Number:
  US08/181,906
• Time in Patent Office: 868 Days
• Field of Search: 437/173, 437/174, 437/21, 437/40, 437/44, 437/907, 437/908
• US Class Current: 438/166
• CPC Class Codes: H01L 21/0242 Crystalline insulating materials
• CPC Class Codes: H01L 21/02422 Non-crystalline insulating materials, e.g. glass, polymers
• CPC Class Codes: H01L 21/02488 Insulating materials
• CPC Class Codes: H01L 21/02532 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/02667 Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
• CPC Class Codes: H01L 21/02675 using laser beams
• CPC Class Codes: H01L 21/02686 Pulsed laser beam
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 27/1255 integrated with passive devices, e.g. auxiliary capacitors
• CPC Class Codes: H01L 27/1285 using control of the annealing or irradiation parameters, e.g. using different scanning direction or intensity for different transistors
• CPC Class Codes: H01L 29/42384 for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
• CPC Class Codes: H01L 29/66598 forming drain [D] and lightly doped drain [LDD] simultaneously, e.g. using implantation through the wings a T-shaped layer, or through a specially shaped layer
• CPC Class Codes: H01L 29/66757 Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
• CPC Class Codes: H01L 29/78618 characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure silicide contacts, electrodes in general H01L29/458
• CPC Class Codes: H01L 29/78621 with LDD structure or an extension or an offset region or characterised by the doping profile
• CPC Class Codes: H01L 29/78681 having a semiconductor body comprising AIIIBV or AIIBVI or AIVBVI semiconductor materials, or Se or Te
• CPC Class Codes: H01L 29/78684 having a semiconductor body comprising semiconductor materials of Group IV not being silicon, or alloys including an element of the group IV, e.g. Ge, SiN alloys, SiC alloys H01L29/7869 takes precedence

Abstract

The invention is concerned with the fabrication of a MIS semiconductor device of high reliability by using a low-temperature process. Disclosed is a method of fabricating a MIS semiconductor device, wherein doped regions are selectively formed in a semiconductor substrate or a semiconductor thin film, provisions are then made so that laser or equivalent high-intensity light is radiated also onto the boundaries between the doped regions and their adjacent active region, and the laser or equivalent high-intensity light is radiated from above to accomplish activation.

Claims

1. A method of fabricating a MIS semiconductor device comprising the steps of:

forming a mask on a semiconductor;

forming impurity regions by introducing impurities selectively into a the semiconductor using said mask;

removing said mask;

increasing the crystallinity of at least said impurity regions by irradiating said semiconductor with light after the removing of said mask; and

forming a gate electrode on a portion of said semiconductor located between said impurity regions with an insulating film between said portion and said gate electrode after said increasing step,

wherein said mask has a width wider than said gate electrode in a direction from one of said impurity regions to the other one of said impurity regions.

2. The method of claim 1 wherein said light is a laser light or a light equivalent to a laser light.

3. The method of claim 1 wherein said light is emitted from a light source selected from the group consisting of a coherent light source and an incoherent light source.

4. A method of fabricating a MIS semiconductor device comprising the steps of:

forming a connection of conductive material on a semiconductor with an insulating film interposed therebetween;

introducing impurities in self-aligned fashion into said semiconductor by using said connection as a mask to form impurity regions in the semiconductor;

etching both ends of said connection after the impurity introduction to expose boundaries been said impurity regions and an active region formed therebetween; and

increasing the crystallinity of said impurity regions and the boundaries by irradiating with light.

5. The method of claim 4 wherein said light is a laser light or a light equivalent to a laser light.

6. The method of claim 4 wherein said light is emitted from a light source selected from the group consisting of a coherent light source and an incoherent light source.

7. The method of claim 4 further comprising the step of anodizing said connection after the light irradiation.

8. A method of fabricating a MIS semiconductor device comprising the steps of:

forming a connection of anodizable conductive material on top of a semiconductor with a mask with an insulating film interposed between said connection and said semiconductor;

anodizing the surface of the connection;

introducing impurities into regions of said semiconductor by using as a mask said connection processed in the anodizing step;

removing said connection to expose said impurity introduced regions and an active region sandwiched by said impurity introduced regions, and

increasing the crystallinity of at least said impurity introduced regions by irradiating with light; and

forming a connection by using a mask having the same pattern as said mask used in said forming step.

9. The method of claim 8 wherein said light is a laser light or a light equivalent to a laser light.

10. The method of claim 8 wherein said light is emitted from a light source selected from the group consisting of a coherent light source and an incoherent light source.

16. The device of claim 8 wherein offset regions are formed by the second forming step.

11. A method of fabricating a MIS semiconductor device comprising the steps of:

forming a connection of conductive material on an active region of a semiconductor with an insulating film interposed therebetween;

forming a coating film selectively on said connection;

introducing impurities in self-aligned fashion into said semiconductor by using as a mask said connection having formed thereon said coating film to form impurity regions sandwiching said active region in said semiconductor;

removing at least a portion of the coating film after the impurity introduction to expose the boundary between said active region and each of said impurity regions or at least a part of the vicinity of said boundary; and

increasing the crystallinity of at least said impurity regions by irradiating with light after said removing step.

12. The method of claim 11 further comprising the step of anodizing said connection after said improving step.

13. The method of claim 11 wherein said light is a laser light or a light equivalent to a laser light.

14. The method of claim 11 wherein said light is emitted from a light source selected from the group consisting of a coherent light source and an incoherent light source.

15. Method of manufacturing an electric device comprising the steps of:

forming a first wiring comprising an anodizable material on a substrate, said wiring having at least one connection portion;

forming an organic mask on said connection portion of said conductive wiring;

anodic oxidizing said first wiring in order to form an anodic oxide layer thereon other than on said connection portion;

removing said organic mask after anodic oxidizing;

forming an interlayer insulator over said wiring;

forming a contact hole through said interlayer insulator to expose said connection portion of the first wiring;

forming a second wiring on said interlayer insulator where said second wiring contacts said connection portion of said first wiring through the contact hole of said interlayer insulator.