Active device constructed in opening formed in insulation layer

• US 5,523,600 A
• Filed: 10/26/1994
• Issued: 06/04/1996
• Est. Priority Date: 11/01/1993
• Status: Expired due to Term

• Current Assignee: LSI Logic Corporation (Broadcom, Inc.)
• Original Assignee: LSI Logic Corporation (Broadcom, Inc.)
• Inventors: Kapoor, Ashok K.
• Primary Examiner(s): Hille, Rolf
• Assistant Examiner(s): TRAN, MINH LOAN
• Application Number:
  US08/330,062
• Time in Patent Office: 587 Days
• Field of Search: 257/328, 257/329, 257/330, 257/351, 257/369, 257/379, 257/380, 257/622, 257/903, 257/904, 257/377, 257/758, 257/754, 257/383, 257/334, 257/536, 257/537, 257/538
• US Class Current: 257/330
• CPC Class Codes: H01L 29/6675 Amorphous silicon or polysilicon transistors
• CPC Class Codes: H01L 29/7833 with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's for thin film transistors H01L29/78618
• CPC Class Codes: H10B 10/125 the MOSFET being a thin film transistor [TFT]
• CPC Class Codes: Y10S 257/904 with passive components,, e.g. polysilicon resistors

Abstract

A compact MOS type active device is constructed at least partially in an opening in an insulation layer, such as an oxide layer, above a portion of a semiconductor substrate forming a first source/drain region of the MOS type active device. A semiconductor material, on the sidewall of the opening, and in electrical communication with the portion of the substrate forming the first source/drain region of the device, comprises the channel portion of the MOS device. A second source/drain region, in communication with an opposite end of the channel, is formed on the insulation layer adjacent the opening and in electrical communication with the channel material in the opening. A gate oxide layer is formed over the channel portion and at least partially in the opening, and a conductive gate electrode is then formed above the gate oxide.

Claims

1. An integrated circuit structure comprising first and second MOS type active device with said first MOS type active device at least partially constructed in a first opening in an insulation layer over a semiconductor substrate comprising:

a) a first source/drain region formed in said semiconductor substrate below said first opening in said insulation layer;

b) a semiconductor material, formed on the sidewall of said opening and comprising a channel portion of said first MOS device, and in electrical communication, at one end thereof, with said first source/drain region in said substrate;

c) a second source/drain region, in electrical communication with an opposite end of said channel portion, formed on said insulation layer adjacent said opening therein;

d) a gate oxide layer formed over said channel portion of said first MOS device; and

e) a gate electrode formed over said gate oxide and said second MOS type active device is formed in said semiconductor substrate with a first source/drain region common with said first source/drain region of said first MOS type active device at least partially constructed in said first opening in said insulation layer.

2. The integrated circuit structure of claim 1 wherein said semiconductor material formed on said sidewall of said opening comprises a polycrystalline semiconductor material formed by deposition and etchback.

3. The integrated circuit structure of claim 1 wherein a resistor is formed in a second opening in said insulation layer and one end of said resistor is in electrical communication with said first source/drain region of said first MOS type active device at least partially formed in said first opening in said insulator layer.

4. The integrated circuit structure of claim 1 wherein a resistor is formed in a second opening in said insulation layer and one end of said resistor is in electrical communication with said common first source/drain regions of said first and second MOS type active devices.

5. The integrated circuit structure of claim 1 wherein a first metal layer is formed over said insulation layer, a second insulation layer is formed over said first metal layer, a second metal layer is formed over said second insulation layer, and a resistor is formed in a via in said second insulation layer between said first metal layer and said second metal layer, and one end of said resistor is in electrical communication with said common first source/drain regions of said first and second MOS type active devices.

6. The integrated circuit structure of claim 5 wherein at least one of said metal layers is a refractory metal layer.

7. An integrated circuit structure comprising first and second MOS type active devices at least one of which is at least partially constructed in a first opening in an insulation layer over a semiconductor substrate, said first MOS device comprising:

a) a first source/drain region formed in said semiconductor substrate below said first opening in said insulation layer;

b) a semiconductor material, formed on the sidewall of said first opening and comprising a channel portion of said first MOS device, and in electrical communication, at one end thereof, with said first source/drain region in said substrate;

c) a second source/drain region, in communication with an opposite end of said channel portion, formed on said insulation layer adjacent said first opening therein and in electrical communication with an opposite end of said channel portion formed therein;

d) a gate oxide layer formed over said channel portion of said first MOS device; and

e) a gate electrode formed over said gate oxide; and

said second MOS device comprising;

a) a first source/drain region common to said first source/drain region of said first MOS device;

b) a channel region formed in said substrate adjacent said first source/drain region in said substrate;

c) a gate oxide formed over said channel region in said substrate;

d) a gate electrode formed over said gate oxide formed over said channel region in said substrate; and

e) a second source/drain region formed in said substrate adjacent an opposite end of said channel region formed in said substrate.

8. The structure of claim 7 wherein said integrated circuit structure further comprises a third MOS type active device formed in a second opening in said insulation layer, said third MOS type active device comprising:

a) a first source/drain region common to said common first source/drain region of said first and second MOS devices;

b) a semiconductor material, formed on the sidewall of said second opening and comprising a channel portion of said third MOS device, and in electrical communication, at one end thereof, with said common first source/drain region in said substrate;

c) a second source/drain region, in communication with an opposite end of said channel portion of said third MOS type active device, formed on said insulation layer adjacent said second opening therein and in electrical communication with an opposite end of said channel portion formed therein;

d) a gate oxide layer formed over said channel portion of said third MOS device; and

e) a gate electrode formed over said gate oxide.

9. The integrated circuit structure of claim 7 wherein a resistor is formed in a second opening in said insulation layer and one end of said resistor is in electrical communication with said common first source/drain region of said first and second MOS type active devices.

10. The integrated circuit structure of claim 7 wherein a metal layer is formed over said insulation layer, a second insulation layer is formed over said metal layer, a resistor is formed in an opening in said second insulation layer, and one end of said resistor is in electrical communication with said common first source/drain region of said first and second MOS type active devices.

11. An integrated circuit structure comprising first and second MOS type active devices which are at least partially constructed respectively in spaced apart first and second generally cylindrical openings in an insulation layer on a semiconductor substrate, said first MOS device comprising:

a) a first source/drain region formed in said semiconductor substrate below said first opening in said insulation layer;

b) a semiconductor material, formed on the entire sidewall of said first generally cylindrical opening in said insulation layer and comprising a channel portion of said first MOS device, and in electrical communication, at one end thereof, with said first source/drain region in said substrate;

c) a second source/drain region, formed over said insulation layer adjacent said first opening therein and in electrical communication with an opposite end of said channel portion formed therein;

d) a gate oxide layer formed over said channel portion of said first MOS device; and

e) a gate electrode formed over said gate oxide; and

said second MOS device comprising;

a) a first source/drain region common to said first source/drain region of said first MOS device;

b) a semiconductor material, formed on the entire sidewall of said second generally cylindrical opening in said insulation layer and comprising a channel portion of said second MOS device, and in electrical communication, at one end thereof, with said common first source/drain region in said substrate;

c) a second source/drain region, in communication with an opposite end of said channel portion of said second MOS type active device, formed over said insulation layer adjacent said second opening therein and in electrical communication with an opposite end of said channel portion formed in said second opening in said insulation layer;

d) a gate oxide layer formed over said channel portion of said second MOS device; and

e) a gate electrode formed over said gate oxide.

12. An integrated circuit structure comprising first, second, and third MOS type active devices at least two of which are at least partially constructed respectively in first and second openings in an insulation layer on a semiconductor substrate, said first MOS device comprising:

a) a first source/drain region formed in said semiconductor substrate below said first opening in said insulation layer;

b) a semiconductor material, formed on the sidewall of said first opening in said insulation layer and comprising a channel portion of said first MOS device, and in electrical communication, at one end thereof, with said first source/drain region in said substrate;

c) a second source/drain region, in communication with an opposite end of said channel portion, formed on said insulation layer adjacent said first opening therein and in electrical communication with an opposite end of said channel portion formed therein;

d) a gate oxide layer formed over said channel portion of said first MOS device; and

e) a gate electrode formed over said gate oxide;

said second MOS device comprising;

a) a first source/drain region common to said first source/drain region of said first MOS device;

b) a channel region formed in said substrate adjacent said first source/drain region in said substrate;

c) a gate oxide formed over said channel region in said substrate;

d) a gate electrode formed over said gate oxide formed over said channel region in said substrate; and

e) a second source/drain region formed in said substrate adjacent an opposite end of said channel region in said substrate; and

said third MOS type active device comprising;

a) a first source/drain region common to said common first source/drain region of said first and second MOS devices;

b) a semiconductor material, formed on the sidewall of a second opening in said insulation layer and comprising a channel portion of said third MOS device, and in electrical communication, at one end thereof, with said common first source/drain region in said substrate;

c) a second source/drain region, in communication with an opposite end of said channel portion of said third MOS type active device, formed on said insulation layer adjacent said second opening therein and in electrical communication with an opposite end of said channel portion formed in said second opening in said insulation layer;

d) a gate oxide layer formed over said channel portion of said third MOS device; and

e) a gate electrode formed over said gate oxide.

13. An integrated circuit structure including a first insulation layer formed over at least one electrode or doped region of an active device, a first metal layer formed over said first insulation layer and in electrical communication with said one electrode or doped region of said active device through a contact opening formed in said first insulation layer, a second insulation layer formed over said first metal layer, a second metal layer formed over said second insulation layer, a vertical via formed through said second insulation layer from said first metal layer to said second metal layer, and a resistor formed in said vertical via between said first and second metal layers.

14. The integrated circuit structure of claim 13 wherein at least said first metal layer comprises a refractory metal layer.

15. An integrated circuit structure comprising first, second, and third MOS type active devices with said first and second MOS type active devices at least partially constructed in first and second openings in an insulation layer over a semiconductor substrate comprising:

a) a first MOS device comprising;

i) a first source/drain region formed in said semiconductor substrate below said first opening in said insulation layer;

ii) a semiconductor material, formed on the sidewall of said opening and comprising a channel portion of said first MOS device, and in electrical communication, at one end thereof, with said first source/drain region in said substrate;

iii) a second source/drain region, in electrical communication with an opposite end of said channel portion, formed on said insulation layer adjacent said opening therein;

iv) a gate oxide layer formed over said channel portion of said first MOS device; and

v) a gate electrode formed over said gate oxide;

b) a second MOS type active device formed at least partially in a second opening in said insulation layer over said semiconductor substrate with a first source/drain region of said second MOS type active device common with said first source/drain region of said first MOS type active device; and

c) a third MOS type active device formed in said semiconductor substrate with a first source/drain region common with said first source/drain regions of both of said first and second MOS type active devices respectively formed at least partially in said first and second openings in said insulation layer.