Semiconductor integrated device having parallel signal lines

• US 5,523,622 A
• Filed: 09/25/1995
• Issued: 06/04/1996
• Est. Priority Date: 11/24/1992
• Status: Expired due to Fees

• Current Assignee: Hitachi, Ltd., Hitachi ULSI Engineering Corp
• Original Assignee: Hitachi, Ltd., Hitachi ULSI Engineering Corp
• Inventors: Yoshihara, Kazuhiro, Hayashi, Kiyoshi, Masuzawa, Kazutaka, Kumazawa, Jun, Harada, Takashi, Nagai, Kenji, Kamada, Chiyoshi, Nishiuma, Masahiko
• Primary Examiner(s): Limanek, Robert P.
• Assistant Examiner(s): Hardy, David B.
• Application Number:
  US08/533,410
• Time in Patent Office: 253 Days
• Field of Search: 257/773, 257/777, 257/778, 257/737, 257/750, 257/664, 257/738, 257/698, 257/735, 257/734, 257/686, 257/704
• US Class Current: 257/734
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 2224/16235 the bump connector connecting to a via metallisation of the item
• CPC Class Codes: H01L 2224/73253 Bump and layer connectors
• CPC Class Codes: H01L 23/13 characterised by the shape
• CPC Class Codes: H01L 23/49822 Multilayer substrates multilayer metallisation on monolayer substrate H01L23/498
• CPC Class Codes: H01L 23/66 High-frequency adaptations
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01079 Gold [Au]
• CPC Class Codes: H01L 2924/1305 Bipolar Junction Transistor [BJT]
• CPC Class Codes: H01L 2924/15153 the die mounting substrate comprising a recess for hosting the device
• CPC Class Codes: H01L 2924/1517 Multilayer substrate
• CPC Class Codes: H01L 2924/15173 in a single layer of the multilayer substrate
• CPC Class Codes: H01L 2924/16195 Flat cap [not enclosing an internal cavity]
• CPC Class Codes: H01L 2924/3011 Impedance

Abstract

For taking a characteristic impedance matching of signal transmission lines in a package which carries thereon a semiconductor chip with a very high-speed LSI formed thereon, there is provided a semiconductor integrated circuit device wherein one ends of signal transmission lines formed on a main surface of a package substrate are extended up to the position just under pads formed on a main surface of the semiconductor chip and are connected to the pads on the chip electrically through bump electrodes, while opposite ends of the signal transmission lines are extended to the outer peripheral portion of the main surface of the package substrate and outer leads are bonded thereto.

Claims

1. A mounting structure for a semiconductor integrated device comprising:

a first substrate having;

a first substantially flat surface and a second substantially flat surface opposite said first substantially flat surface;

a central cavity formed in said first substantially flat surface toward said second substantially flat surface;

first signal transmission lines formed on said first substantially flat surface, each of said first signal transmission lines having a first end portion which is adjacent to said cavity;

an electronic package having;

a second substrate having a third substantially flat surface;

second signal transmission lines formed on said third substantially flat surface, each of said second signal transmission lines having a first end portion and a second end portion;

a semiconductor chip having a main surface, said semiconductor chip including electrode pads on said main surface thereof, said semiconductor chip being mounted on said second substrate with said main surface of said semiconductor chip opposed to said third substantially flat surface of said second substrate, said first end portions of said second signal transmission lines being electrically connected to said electrode pads through bump electrodes; and

leads bonded to a peripheral portion of said second substrate and protruding from said second substrate, said leads being electrically connected to said second end portions of said second signal transmission lines and extending substantially parallel to said second signal transmission lines;

wherein at least one of said first end portions of said second signal transmission lines extends under said electrode pads located in a central area of said semiconductor chip and is electrically connected to one of said electrode pads, wherein said electronic package is mounted in said cavity of said first substrate, and wherein each of said leads of said electronic package is electrically connected to said first end portion of each of said first transmission lines and extends substantially parallel to said first transmission lines.

2. A mounting structure according to claim 1, further comprising earth conductors formed on said third substantially flat surface of said second substrate, wherein said earth conductors are formed between said second signal transmission lines.

3. A mounting structure according to claim 1, wherein said semiconductor chip includes a clock input buffer circuit formed on said central area of said main surface thereof, and wherein said clock input buffer is electrically coupled to said one of said electrode pads.

4. A mounting structure according to claim 3, wherein said semiconductor chip includes an input signal terminating resistor and a capacitor element coupled to one end of said input signal terminating resistor, formed on said main surface thereof, and wherein the other end of said input signal terminating resistor is electrically coupled to said clock input buffer circuit.

5. A mounting structure according to claim 1, wherein said second substrate includes a first insulating layer, a second insulating layer formed on said first insulating layer and a third insulating layer formed on said second insulating layer, wherein a first earth conductor plate is formed between said second and third insulating layers, a power source plate is formed between said first and second insulating layers, and second earth conductor plate is formed on a back surface of said first insulating layer, and wherein said first and second earth conductor plates are electrically connected to each other via through hole formed in said first and second insulating layers, and an upper surface of said third insulating layer corresponding to said third substantially flat surface of said second substrate.

6. A mounting structure for a semiconductor integrated circuit device comprising:

a first substantially flat surface and a second substantially flat surface opposite to said first substantially flat surface;

a cavity formed to cave from said first substantially flat surface toward said second substantially flat surface;

first signal transmission lines formed on said first substantially flat surface, each of said first signal transmission lines having a first end portion which is adjacent to said cavity;

an electronic package having;

a substrate having a third substantially flat surface;

second signal transmission lines formed on said third substantially flat surface, each of said second signal transmission lines having a first end portion and a second end portion;

a semiconductor chip having a main surface, said semiconductor chip including electrode pads on said main surface thereof, said semiconductor chip being mounted on said substrate in such a manner that said main surface of said semiconductor chip is opposed to said third substantially flat surface of said substrate, said first end portions of said second signal transmission lines being electrically connected with said electrode pads through bump electrodes;

a cap member formed over said substrate so as to cover said semiconductor chip; and

leads protruding from a peripheral portion of said substrate, said leads being electrically connected with said second end portions of said second signal transmission lines and extending substantially parallel to said second signal transmission lines,

wherein said electronic package is mounted in said cavity of said mounting substrate, and wherein each of said leads of said electronic package is electrically connected with said first end portion of each of said first signal transmission lines and extends substantially parallel to said first signal transmission lines.

7. A mounting structure according to claim 6 wherein a rear surface of said semiconductor chip and said cap member are bonded to each other by a solder material.