Component insensitive, analog bandpass filter
First Claim
Patent Images
1. An analog bandpass filter comprising:
- (A) an analog subtractor connected for receiving, at a plus input terminal, an analog input signal;
(B) a first delay element, connected for receiving a subtracted analog signal from the subtractor, for delaying the subtracted analog signal for one delay interval determined by a digital clock;
(C) a second delay element, connected for receiving a first delayed analog signal from the first delay element, and connected for delivering a second delayed analog signal to a minus input terminal of the subtractor, for delaying the signal for another delay interval determined by the digital clock; and
(D) an output terminal of said filter connected for producing analog output signals located at an output terminal of one of a group consisting of the subtractor, the first delay element, and the second delay element;
wherein;
(a) the clock is a two phase non-overlapping clock;
(b) at least one of the delay elements comprises a first half-delay element and a second half-delay element, each half delay-element being configured for delaying the input along signal for one-half of the delay interval determined by the clock; and
(c) the output terminal of said delay element is located at an output terminal of a group consisting of the first half-delay element and the second half-delay element.
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Abstract
A digitally driven, analog bandpass filter has an analog summer and two analog delay elements connected in a loop. An input signal to the filter is applied to a plus input terminal of the summer, and the output of the second delay elements is applied to a minus input terminal of the summer. The output of filter may be taken either from the output of the summer, or from the output of the second delay element, or from any point in between. Each delay element is driven by a two phase non-overlapping clock, and each element passes a charge from a first capacitor through an op amp to either a second capacitor (first phase) or a third capacitor (second phase). Amplification may be provided by adjusting the ratio of the second (or third) capacitor to the first capacitor. If a differential op amp is used, both sides of the op amp are clocked together, and each side has its own trio of capacitors identical to the trio on the other side. The passband is centered precisely on one-quarter of the clock frequency, and does not vary with manufacturing variances in the components of the filter.
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Citations
5 Claims
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1. An analog bandpass filter comprising:
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(A) an analog subtractor connected for receiving, at a plus input terminal, an analog input signal; (B) a first delay element, connected for receiving a subtracted analog signal from the subtractor, for delaying the subtracted analog signal for one delay interval determined by a digital clock; (C) a second delay element, connected for receiving a first delayed analog signal from the first delay element, and connected for delivering a second delayed analog signal to a minus input terminal of the subtractor, for delaying the signal for another delay interval determined by the digital clock; and (D) an output terminal of said filter connected for producing analog output signals located at an output terminal of one of a group consisting of the subtractor, the first delay element, and the second delay element; wherein; (a) the clock is a two phase non-overlapping clock; (b) at least one of the delay elements comprises a first half-delay element and a second half-delay element, each half delay-element being configured for delaying the input along signal for one-half of the delay interval determined by the clock; and (c) the output terminal of said delay element is located at an output terminal of a group consisting of the first half-delay element and the second half-delay element. - View Dependent Claims (2, 3)
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4. An analog bandpass filter comprising:
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(A) a plus analog subtractor connected for receiving, at a plus input terminal, an analog input signal of a plus polarity; (B) a first plus delay element, connected for receiving a subtracted analog signal from the plus analog subtractor, for delaying the subtracted analog signal for one delay interval determined by a digital clock; (C) a second plus delay element, connected for receiving a first delayed analog signal from the first plus delay element, and connected for delivering a second delayed analog signal to a minus input terminal of the plus analog subtractor, for delaying the first delayed analog signal for another delay interval determined by the digital clock; (D) a plus output terminal of said filter connected for producing plus analog output signals located at an output terminal of one of a group consisting of the plus analog subtractor, the first plus delay element, and the second plus delay element; (E) a minus analog subtractor connected for receiving, at a minus input terminal, a differential analog input signal of a minus polarity; (F) a first minus delay element, connected for receiving a subtracted analog signal from the minus analog subtractor, for delaying the subtracted analog signal for one delay interval determined by the digital clock; (G) a second minus delay element, connected for receiving a first delayed analog signal from the first minus delay element, and connected for delivering a second delayed analog signal to a minus input terminal of the minus analog subtractor, for delaying the first delayed analog signal for delay interval determined by the digital clock; and (H) a minus output terminal of said filter connected for producing analog output signals located at an output terminal of one of a group consisting of the minus analog subtractor, the first minus delay element, and the second minus delay element; wherein; (a) the clock is a two phase non-overlapping clock; (b) at least one of the delay elements comprises a first half-delay element and a second half-delay element, each half delay-element being configured for delaying the input analog signal for one-half of the delay interval determined by the clock; and (c) the output terminal of said delay element is located at an output terminal of a group consisting of the first half-delay element and the second half-delay clement. - View Dependent Claims (5)
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Specification
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Current AssigneeSkyworks Solutions Incorporated
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Original AssigneeRockwell International Corporation
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InventorsLongo, Lorenzo L., Halim, Raouf, Horng, Bor-Rong
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Primary Examiner(s)Callahan, Timothy P.
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Assistant Examiner(s)LE, DINH THANH
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Application NumberUS08/196,328Time in Patent Office840 DaysField of Search307/520, 307/521, 307/603, 307/159, 307/127, 328/167, 328/165, 328/166, 328/154, 333/166, 333/173, 327/103, 327/551, 327/554, 327/557, 327/45, 327/94, 327/552, 327/561, 330/107, 330/109US Class Current327/557CPC Class CodesH03H 19/004 Switched capacitor networksH03M 3/404 characterised by the type o...H03M 3/458 Analogue/digital converters...
