Digital quadriphase-shift keying modulator

• US 5,523,726 A
• Filed: 10/13/1994
• Issued: 06/04/1996
• Est. Priority Date: 10/13/1994
• Status: Expired due to Term

• Current Assignee: iBiquity Digital Corporation (Adeia Inc.)
• Original Assignee: Westinghouse Electric Company LLC (Brookfield Asset Management Incorporated)
• Inventors: Kroeger, Brian W., Stehlik, Roy
• Primary Examiner(s): MIS, DAVID C
• Application Number:
  US08/322,833
• Time in Patent Office: 600 Days
• Field of Search: 332/103-105, 375/279-284, 375/308
• US Class Current: 332/103
• CPC Class Codes: H04L 27/2092 with digital generation of the modulated carrier (does not include the modulation of a digitally generated carrier)

Abstract

A digital quadriphase-shift keying modulator is described which generates a modulated intermediate carrier frequency (IF) based on a desired number of samples for each input information bit. The design includes a ROM (or RAM) look-up table which stores digitized waveforms. The inphase and quadrature components of a complex baseband signal are translated to an IF at a multiple of the sampling rate simply by alternating the inphase and quadrature samples and alternating signs. The real IF output is produced by summing the inphase and quadrature signals.

Claims

1. A method of modulating binary data sequences, each having a plurality of symbols occurring at a symbol frequency, to an intermediate carrier frequency, and a ROM having a plurality of stored digital waveforms including a plurality of digitized samples and corresponding to one of a plurality of outputs of a filter in response to a plurality of combinations of symbol inputs having a predetermined span of symbols, said method comprising the steps of:

inputting, in parallel, first and second data sequences at the symbol frequency;

multiplexing an M number of symbols from each sequence at a sample frequency, the sample frequency being the intermediate carrier frequency divided by four to produce a multiplexed train of successive groups of the M number of symbols, in parallel, from first and second data sequences;

inverting every other pair of successive groups of the multiplexed train to form successive first portions of an address from successive inverted and non-inverted groups of the multiplexed train;

forming successive second portions of the address in accordance with a position of one of the groups in the inverted and non-inverted groups of the multiplexed train;

outputting from the ROM contents of a storage location corresponding a combination of the first and second portions of the address, so that for each parallel input from the first and second data sequences, a number of digital samples, corresponding to the sample frequency, are read out from the ROM at the intermediate carrier frequency; and

converting the ROM outputs to an analog signal at the intermediate carrier frequency.

2. The method according to claim 1, wherein the M number of symbols multiplexed from first and second data sequences is equal to the predetermined span of symbols.

3. The method according to claim 1, wherein the predetermined span is 3 symbols.

4. The method according to claim 1, wherein the predetermined span is 5 symbols.

5. The method according to claim 1, wherein the ROM has only a real portion of the digital waveforms stored.

6. The method according to claim 1, wherein the intermediate carrier frequency is one-quarter of the sample frequency.

7. A modulator for modulating data sequences, each having a plurality of symbols occurring at a symbol frequency, to a carrier frequency, and a ROM having a plurality of stored digital waveforms including a plurality of digitized samples and corresponding to one of a plurality of outputs of a filter in response to a plurality of combinations of symbol inputs having a predetermined span of symbols, said digital modulator comprising:

serial to parallel input means for serially inputting, in parallel, first and second data sequences at the symbol frequency and outputting, in parallel, an M number of symbols from both trains;

a multiplexer for multiplexing the M number of symbols from each data sequence at a sample frequency, the sample frequency being an intermediate carrier frequency divided by four to produce a multiplexed train of successive groups of the M number of symbols, in parallel, from first and second data sequences;

an inverter for inverting every other pair of successive groups of the multiplexed train to form successive first portions of an address from successive inverted and non-inverted groups of the multiplexed train;

counting means for determining a position of one of the groups in the inverted and non-inverted groups of the multiplexed train corresponding to the first portion of the address;

address forming means forming successive second portions of the address from the position of the one of the groups in the inverted and non-inverted groups of the multiplexed train corresponding to the first portion of the address;

a ROM for outputting contents of a storage location corresponding to a combination of the first and second portions of the address, so that for each parallel input from the first and second data sequences, a number of digital samples, corresponding to the sample frequency, are read out from the ROM at the intermediate carrier frequency;

a digital-to-analog converter for converting the ROM outputs to an analog signal at the intermediate carrier frequency; and

an up-converter for converting the analog signal to a carrier frequency.

8. The modulator according to claim 7, wherein the M number of symbols multiplexed from first and second data sequences is equal to the predetermined span of symbols.

9. The modulator according to claim 7, wherein the predetermined span is 3 symbols.

10. The modulator according to claim 7, wherein the predetermined span is 5 symbols.

11. The modulator according to claim 7, wherein the ROM has only a real portion of the digital waveforms stored.

12. The modulator according to claim 7, wherein the intermediate carrier frequency is one-quarter of the sample frequency.

13. A digital quadriphase-shift keying modulator, comprising:

a counter responsive to a clock signal for outputting successive pluralities of bits which represent successive values of the counter;

a first serial-to-parallel converter for receiving a plurality of first symbols in serial fashion and outputting a predetermined number of the plurality of first symbols in parallel fashion in response to a first bit of one of the successive pluralities of bits output by the counter;

a second serial-to-parallel converter for receiving a plurality of second symbols in serial fashion and outputting a predetermined number of the plurality of second symbols in parallel fashion in response to the first bit of the successive pluralities of bits output by the counter;

a multiplexer for selecting between the output of the first serial-to-parallel converter and the output of the second serial-to-parallel converter in response to a second bit of the successive pluralities of bits output by the counter;

sign changing means for changing a sign of the output selected by the selecting means in response to a third bit of the successive pluralities of bits output by the counter; and

a memory for storing a plurality of digital samples of a waveform and outputting one of the plurality of digital samples in response to an address, wherein the address includes the output of the counter and the output of the multiplexer.

14. The apparatus of claim 13, further comprising:

a digital-to-analog converter for converting the output of the memory into a first analog signal of a predetermined frequency.

15. The apparatus of claim 13, wherein the plurality of bits output in parallel from each of the first and second serial-to-parallel converters is equal in number to a predetermined span of an impulse response.

16. The apparatus according to claim 15, wherein the predetermined span of the impulse span is 5.

17. The apparatus of claim 13, wherein the multiplexer selects the output from the second serial-to-parallel converter for an odd counter value and selects the output of the first serial-to-parallel converter for an even counter value, and

wherein the sign means changes the sign of the output selected by the selecting means when a bit representing a 2¹ power of the plurality of bits of the counter value is in a high state.

18. The apparatus of claim 13, wherein one of the plurality of digital samples output from the memory comprises a predetermined number of bits according to a desired resolution.

19. A method for communicating with a satellite comprising the steps of:

receiving first signals from the satellite in the form of first modulated signals;

demodulating the first modulated signals to produce first demodulated signals;

outputting the first demodulated signals;

generating first and second data sequences, each having a plurality of symbols occurring at a symbol frequency to be transmitted;

modulating the first and second data sequences for transmission to a carrier frequency, utilizing a ROM having a plurality of stored digital waveforms including a plurality of digitized samples and corresponding to one of a plurality of outputs of a filter in response to a plurality of combinations of symbol inputs having a predetermined span of symbols, said modulating comprising the substeps of;

inputting, in parallel, first and second data sequences at the symbol frequency;

multiplexing an M number of symbols from each train at a sample frequency, the sample frequency being an intermediate carrier frequency divided by four to produce a multiplexed train of successive groups of the M number of symbols, in parallel, from first and second data sequences;

inverting every other pair of successive groups of the multiplexed train to form successive first portions of an address from successive inverted and non-inverted groups of the multiplexed train;

forming successive second portions of the address in accordance with a position of one of the groups in the inverted and non-inverted groups of the multiplexed train;

outputting from the ROM contents of a storage location corresponding a combination of the first and second portions of the address, so that for each parallel input from the first and second data sequences, a number of digital samples, corresponding to the sample frequency, are read out from the ROM at the intermediate carrier frequency; and

converting the ROM outputs to an analog signal at the intermediate carrier frequency;

up-converting the analog signal to the carrier frequency; and

transmitting the up-converted signal to the satellite.

20. The method according to claim 19, wherein the M number of pulses multiplexed from first and second data sequences is equal to the predetermined span of symbols.

21. The method according to claim 19, wherein the predetermined span is 3 symbols.

22. The method according to claim 19, wherein the predetermined span is 5 symbols.

23. The method according to claim 19, wherein the ROM has only a real portion of the digital waveforms stored.

24. The method according to claim 19, wherein the intermediate carrier frequency is one-quarter of the sample frequency.

25. A mobile terminal unit for receiving from, and transmitting to, a satellite comprising;

receiving means for receiving signals from the satellite;

demodulating means for demodulating the received signals;

modulating means for modulating first and second data sequences, each data sequence having a plurality of symbols occurring at a symbol frequency, to an intermediate carrier frequency, said modulating means comprising;

a ROM having a plurality of stored digital waveforms including a plurality of digitized samples and corresponding to one of a plurality of outputs of a filter in response to a plurality of combinations of symbol inputs having a predetermined span of symbols;

serial to parallel input means for serially inputting, in parallel, first and second data sequences at the symbol frequency and outputting, in parallel, an M number of symbols from both trains;

a multiplexer for multiplexing the M number of symbols from each train at a sample frequency, the sample frequency being the intermediate carrier frequency divided by four to produce a multiplexed train of successive groups of the M number of symbols, in parallel, from first and second data sequences;

an inverter for inverting every other pair of successive groups of the multiplexed train to form successive first portions of an address from successive inverted and non-inverted groups of the multiplexed train;

counting means for determining a position of one of the groups in the inverted and non-inverted groups of the multiplexed train corresponding to the first portion of the address;

address forming means forming successive second portions of the address from the position of the one of the groups in the inverted and non-inverted groups of the multiplexed train corresponding to the first portion of the address;

a ROM for outputting contents of a storage location corresponding to a combination of the first and second portions of the address, so that for each parallel input from the first and second data sequences, a number of digital samples, corresponding to the sample frequency, are read out from the ROM at the intermediate carrier frequency; and

a digital-to-analog converter for converting the ROM outputs to an analog signal at the intermediate carrier frequency; and

an up-converter for converting the modulated first and second pulse trains to a carrier frequency.

26. The mobile terminal unit according to claim 25, wherein the M number of pulses multiplexed from first and second data sequences is equal to the predetermined span of symbols.

27. The mobile terminal unit according to claim 25, wherein the predetermined span is 3 symbols.

28. The mobile terminal unit according to claim 25, wherein the predetermined span is 5 symbols.

29. The mobile terminal unit according to claim 25, wherein the ROM has only a real portion of the digital waveforms stored.

30. The mobile terminal unit according to claim 25, wherein the intermediate carrier frequency is one-quarter of the sample frequency.