DMD architecture and timing for use in a pulse-width modulated display system

• US 5,523,803 A
• Filed: 06/08/1994
• Issued: 06/04/1996
• Est. Priority Date: 04/01/1991
• Status: Expired due to Term

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Sampsell, Jeffrey B., Urbanus, Paul M.
• Primary Examiner(s): METJAHIC, SAFET
• Assistant Examiner(s): Cohen, Cheryl
• Application Number:
  US08/255,610
• Time in Patent Office: 727 Days
• Field of Search: 348/714-719, 348/759, 348/771, 345/147, 345/148, 345/96, 345/98, 345/100, 345/197
• US Class Current: 348/771
• CPC Class Codes: G09G 2310/0205 Simultaneous scanning of several lines in flat panels
• CPC Class Codes: G09G 2310/061 for resetting or blanking
• CPC Class Codes: G09G 2352/00 Parallel handling of streams of display data
• CPC Class Codes: G09G 2360/18 Use of a frame buffer in a display terminal, inclusive of the display panel
• CPC Class Codes: G09G 3/2018 by time modulation using two or more time intervals
• CPC Class Codes: G09G 3/2022 using sub-frames
• CPC Class Codes: G09G 3/2037 with specific control of sub-frames corresponding to the least significant bits
• CPC Class Codes: G09G 3/2092 Details of a display terminals using a flat panel, the details relating to the control arrangement of the display terminal and to the interfaces thereto suitable for both CRT and flat panel G09G5/003; specific for a CRT G09G1/165
• CPC Class Codes: G09G 3/346 based on modulation of the reflection angle, e.g. micromirrors micromirrors devices per se G02B26/0833
• CPC Class Codes: G09G 5/39 Control of the bit-mapped memory
• CPC Class Codes: G09G 5/393 Arrangements for updating the contents of the bit-mapped memory
• CPC Class Codes: G09G 5/395 Arrangements specially adapted for transferring the contents of the bit-mapped memory to the screen G09G5/399 takes precedence
• CPC Class Codes: G09G 5/399 using two or more bit-mapped memories, the operations of which are switched in time, e.g. ping-pong buffers
• CPC Class Codes: H04N 2005/7466 Control circuits therefor
• CPC Class Codes: H04N 3/08 having a moving reflector
• CPC Class Codes: H04N 3/127 using liquid crystals
• CPC Class Codes: H04N 5/7458 the modulator being an array of deformable mirrors, e.g. digital micromirror device [DMD]
• CPC Class Codes: H04N 9/30 using solid-state colour display devices

Abstract

It is possible to replace a standard tuning unit in a television with spatial light modulator circuitry to improve the resolution seen by the viewer. The invention herein provides a system architecture, individual part of the system and techniques for minimizing the burst data rate while maintaining a reasonable system speed. The resultant system provides better resolution with a manageable data rate and bandwidth.

Claims

1. A projection system comprising:

a. a decimation processor comprising at least one input shift register, at least one shadow memory connected to said input shift register, and at least one output shift register connected to said shadow memory;

b. at least one memory cell array for receiving data from said output shift register; and

c. a spatial light modulator for receiving data from said memory cell array.

2. The projection system of claim 1 wherein said at least one memory cell array comprises a first and a second memory cell array.

3. The projection system of claim 2 further comprising a switchable bus connected between said decimation processor and said first and said second memory cell arrays, said bus for alternately connecting said first and said second memory cell array to said decimation processor.

4. The projection system of claim 2 further comprising a switchable bus connected between said first and said second memory cell arrays and said spatial light modulator, said bus for alternately connecting said first and said second memory cell array to said spatial light modulator.

5. The projection system of claim 2 further comprising:

a first switchable bus connected between said decimation processor and said first and said second memory cell arrays, said first switchable bus for alternately connecting said first and said second memory cell array to said decimation processor;

a second switchable bus connected between said first and said second memory cell arrays and said spatial light modulator, said second switchable bus for alternately connecting said first and said second memory cell array to said spatial light modulator; and

wherein said first switchable bus and said second switchable bus are coordinated such that said first memory cell array receives data from said output shift register while said spatial light modulator receives data from said second memory cell array.

6. A decimation processor comprising:

an n-bit wide input bus;

an n-bit wide and m-bit deep input register for receiving a block of data from said input bus, said block of data being comprised of m input data words, each input data word being n-bits wide;

an n-bit wide and m-bit deep shadow RAM for receiving said block of data from said input register; and

an m-bit wide output bus for allowing said block of data to be read out of said shadow RAM in n output words wherein each said output word is m-bits wide and is comprised of one bit from each of said m input words.

7. The decimation processor of claim 6 further comprising:

an output register for receiving said m-bit output word in parallel from said output bus.

8. The decimation processor of claim 7 wherein said output register is an array of i output shift registers each being j-bits wide, said output shift registers receiving said m-bit output words in parallel from said output bus and outputting said m-bits in the form of j output data words, each said output data word being i-bits wide.

9. The decimation processor of claim 7 wherein said output register is a multiplexer.

10. The decimation processor of claim 7 wherein said output register is an array of i

multiplexers, each said multiplexer being j-bits wide, said multiplexers receiving said m-bit output words in parallel from said output bus and outputting said m-bits in the form

of j i-bit output data words.