Testing semiconductor memory device having test circuit

• US 5,523,977 A
• Filed: 05/18/1993
• Issued: 06/04/1996
• Est. Priority Date: 07/13/1989
• Status: Expired due to Term

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Inventors: Nagayama, Yasuji, Tobita, Youichi
• Primary Examiner(s): Beausoliel, Jr., Robert W.
• Application Number:
  US08/062,493
• Time in Patent Office: 1,113 Days
• Field of Search: 371/21.4, 371/21.1, 371/15.1, 365/200, 365/201, 324/73.1
• US Class Current: 365/201
• CPC Class Codes: G11C 11/401 forming cells needing refreshing or charge regeneration, i.e. dynamic cells
• CPC Class Codes: G11C 2029/5004 Voltage
• CPC Class Codes: G11C 29/46 Test trigger logic
• CPC Class Codes: G11C 29/50 Marginal testing, e.g. race, voltage or current testing
• CPC Class Codes: G11C 29/50012 of timing

Abstract

A semiconductor memory device having a test circuit includes voltage detection circuits (120, 220) for detecting a test mode when a voltage higher than a normal use voltage is applied to a terminal (101, 201). When one voltage detection circuit (120) detects a test mode, a voltage switching circuit (130) renders a MOS transistor (111) conductive, a resistance (115) connected in parallel to the MOS transistor is short-circuited and a voltage lower than (1/2·Vcc) is applied to a bit line voltage supply line (9). Alternatively, when the other voltage detection circuit (220) detects the test mode, a voltage switching circuit (230) renders a MOS transistor (211) conductive, a resistance (114) connected in parallel to the MOS transistor is short-circuited, and a voltage higher than (1/2·Vcc) is applied to the bit line voltage supply line. Thus, by applying a voltage higher or lower than that for normal use on a bit line, a memory cell having a small margin can be tested in a short period of time.

Claims

1. A semiconductor memory device having a test circuit, comprising:

a plurality of bit lines;

a plurality of memory cells each including one insulated gate field effect transistor and one capacitance, each insulated gate field effect transistor being connected to a corresponding bit line;

a plurality of input terminals for receiving control signals from an external source;

test mode detecting means operatively connected to said input terminals and responsive to the control signals applied to said input terminals for detecting test mode conditions under which testing of said memory cells is carried out;

voltage switching controlling means responsive to the detection of a test mode by said test mode detecting means for switching between circuit configurations;

voltage generating means, responsive to said voltage switching control means, for generating a first voltage lower than normal operating voltage of said memory cells and a second voltage higher than normal operating voltage of said memory cells; and

means for applying said first and said second voltages to a corresponding bit line.

2. A semiconductor memory device having a test circuit according to claim 1, wherein said test mode detecting means comprises circuit means responsive to a voltage higher than voltage applied to said input terminals during normal memory cell operation, for detecting voltage indicative of said test mode.

3. A semiconductor memory device having a test circuit according to claim 2, wherein

said circuit means for detecting voltage comprises:

a first series circuit having a plurality of first MOS transistors and a first resistance, connected in series between one of said input terminals and a first reference potential;

a second series circuit of a plurality of second MOS transistors and a second resistance connected in series between another of said input terminals and the first reference potential; and

said voltage switching controlling means comprises means for generating a first output voltage in conjunction with said voltage generating means, in response to a second predetermined voltage at a node between a first MOS transistor and said first resistance, and for generating said second voltage in conjunction with said voltage generating means, in response to a second predetermined voltage at a node between a second MOS transistor and said second resistance.

4. A semiconductor memory device having a test circuit according to claim 1, wherein

said test mode detecting means comprises timing detecting means responsive to a control signal being inputted to at least one of said input terminals at a different timing of signals at said input terminals from that used during normal operation of said memory cells for detecting said test mode, and

said voltage switching means comprises means responsive to a detection of a first timing of signals at said input terminals by said timing detecting means for switching to generate said first voltage in conjunction with said voltage generating means, and responsive to a detection of a second timing of signals at said input terminals for switching to generate said second voltage.

5. A semiconductor memory device having a test circuit according to claim 1, wherein

said test mode detecting means comprises means for detecting said test mode, in response to a control signal being inputted to any one of said input terminals at a different timing of signals at said input terminals from that used during normal operation of said memory cells and a voltage higher than normal operating voltage of said memory cells being applied to another of said input terminals, and

said voltages switching means comprises means for switching to generate said first voltage from said voltage generating means in response to an application of said voltage higher than normal operating voltage by said test mode detecting means and a detection of a first timing of signals at said input terminals, and for generating said second voltage in response to a detection of a second timing of signals at said input terminals.

6. A semiconductor memory device having a test circuit according to claim 1, wherein

said voltage generating means comprises:

a first resistance connected between a first reference potential and a first node; and

a second resistance connected between said bit line and said first node,

and wherein said voltage switching controlling means comprises a switching element connected in parallel to said second resistance at said bit line and said first node, said switching element remaining non-conductive under conditions of normal memory cell use and becoming conductive in response to a detection of test mode conditions by said test mode detecting means, said switching element applying said second voltage from said first node to said bit line by shorting said second resistance.

7. A semiconductor memory device having a test circuit according to claim 6, wherein

said voltage generating means further comprises:

a third resistance connected between a second node and said bit line, and

a fourth resistance connected between said second node and a second reference potential,

said voltage switching controlling means comprises a switching element connected in parallel to said third resistance and remaining non-conductive under conditions of normal memory cell use, and becoming conductive in response to a detection of the test mode by said test mode detecting means to apply said first voltage from said second node to said bit line by shorting said third resistance.

8. A semiconductor memory device having a test circuit, comprising:

a plurality of bit lines;

a plurality of memory cells, each including a single transistor and a single capacitance, said transistor being connected to a corresponding bit line;

voltage generating means for generating a voltage to be applied to said bit lines;

means for detecting first and second test mode enable signals for controlling a test mode of said memory device;

means responsive to absence of said first and second test enable signals for controlling said voltage generating means to apply a normal operating voltage of said memory cells to said bit lines;

means responsive to the presence of said

first test enable signal for applying a voltage higher than said normal operating voltage to a corresponding bit line; and

,

means responsive to the presence of said second test enable signal for applying a voltage lower than said normal operating voltage to a corresponding bit line.

9. A semiconductor memory device having a test circuit, said memory device comprising:

a plurality of bit lines;

a plurality of memory cells, each comprising a transistor and a data storage capacitance, said transistor being connected to a corresponding bit line;

sources of first and second reference voltages to be operatively connected to said bit line;

means for detecting first and second test enable signals for controlling a test mode of said memory device;

voltage generating means for generating a third reference voltage to be applied to an electrode of a selected transistor, said third reference voltage having a value between those of said first and second reference voltages to be applied to a bit line corresponding to said selected transistor;

means responsive to absence of said first and second test enable signals for controlling said voltage generating means to apply a normal operating voltage of said memory cells to said corresponding bit line;

means responsive to the presence of said

first test enable signal for applying a voltage higher than said normal operating voltage to a corresponding bit line; and

,

means responsive to the presence of said second test enable signal for applying a voltage lower than said normal operating voltage to a corresponding bit line.

10. A method of operating a semiconductor memory device having a test circuit, said semiconductor memory device comprising sources of first and second reference voltages, a plurality of bit lines, a plurality of memory cells, each memory cell comprising a transistor connected to a corresponding bit line and a data storage capacitance, intermediate potential generating means for applying to a plate of said data storage capacitance a third reference voltage intermediate said first and second reference voltages, and voltage generating means for generating an operating voltage to be applied to said bit lines, said method comprising the steps of:

detecting for first and second testing mode enable signals for controlling a test mode of said memory device;

in response to the absence of said first and second testing mode enable signals, applying a normal operating voltage of said memory cells to a corresponding bit line;

in response to the presence of said first testing mode enable signal, applying a voltage higher than said normal operating voltage of said memory cells to a corresponding bit line; and

,

in response to the presence of said second testing mode enable signal, applying a voltage lower than said normal operating voltage of said memory cell to a corresponding bit line.

11. A semiconductor memory device, comprising:

a memory cell having an insulating gate type field effect transistor having a first main electrode connected to a corresponding bit line and a gate electrode connected to a corresponding word line, and a capacitance having a first electrode connected to a second main electrode of the insulating gate type field effect transistor;

an intermediate potential generating means for applying an intermediate potential between a power supply potential and a ground potential to an output node connected to a second electrode of the capacitance in the memory cell; and

a bit line potential applying means responsive to first and second test mode enable signals for applying to a corresponding bit line the intermediate potential between the power supply potential and the ground potential in a normal operation, a potential higher than the potential of said normal operation upon receiving the first test mode enable signal, and a potential lower than the potential of said normal operation upon receiving the second test mode enable signal.

12. A test circuit of a semiconductor memory device including a memory cell having an insulating gate type field effect transistor having a first main electrode connected to a corresponding bit line and a gate electrode connected to a corresponding word line, and a capacitance having a first electrode connected to a second main electrode of the insulating gate type field effect transistor, and an intermediate potential generating means for applying an intermediate potential between a power supply potential and a ground potential to a first output node connected to a second electrode of the capacitance in the memory cell, said test circuit comprising:

a bit line potential applying means having an intermediate potential generating portion having a second output node for generating a potential for being applied to a corresponding bit line, a first resistance element connected between the second output node and a power supply potential node to which said power supply potential is applied, and a second resistance element connected between said second output node and a ground potential node to which said ground potential is applied, for applying an intermediate potential between said power supply potential and said ground potential to said second output node, and a first transistor connected in parallel to said first resistance element and a second transistor connected in parallel to said second resistance element, for providing an intermediate potential from said intermediate potential generating portion to said second output node with said first and second transistors rendered non-conductive in a normal operation, for providing to said second output node a potential higher than the intermediate potential from said intermediate potential generating portion with said first transistor rendered conductive and said second transistor rendered non-conductive in a first test mode, and for providing to said second output node a potential lower than the intermediate potential from said intermediate potential generating portion with said first transistor rendered non-conductive and said second transistor rendered conductive in a second test mode.

13. A test circuit for a semiconductor memory device including a memory cell having an insulating gate type field effect transistor having a first main electrode connected to a corresponding bit line and a gate electrode connected to a corresponding word line, and a capacitance having a first electrode connected to a second main electrode of the insulating gate type field effect transistor, and an intermediate potential generating means for applying an intermediate potential between a power supply potential and a ground potential to a first output node connected to a second electrode of the capacitance in the memory cell, said test circuit comprising:

a bit line potential applying means having an intermediate potential generating portion having a second output node for generating a potential for being applied to a corresponding bit line, a first resistance element connected between said second output node and a power supply potential node to which said power supply potential is applied, and a second resistance element connected between said second output node and a ground potential node to which said ground potential is applied, for applying an intermediate potential between said power supply potential and said ground potential to said second output node, and a transistor connected in parallel to said second resistance element, for providing to said second output node an intermediate potential from said intermediate potential generating portion with said transistor rendered non-conductive in a normal operation, and for providing to said second output node a potential lower than the intermediate potential from said intermediate potential generating portion with said transistor rendered conductive in a test mode.