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Testing semiconductor memory device having test circuit

  • US 5,523,977 A
  • Filed: 05/18/1993
  • Issued: 06/04/1996
  • Est. Priority Date: 07/13/1989
  • Status: Expired due to Term
First Claim
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1. A semiconductor memory device having a test circuit, comprising:

  • a plurality of bit lines;

    a plurality of memory cells each including one insulated gate field effect transistor and one capacitance, each insulated gate field effect transistor being connected to a corresponding bit line;

    a plurality of input terminals for receiving control signals from an external source;

    test mode detecting means operatively connected to said input terminals and responsive to the control signals applied to said input terminals for detecting test mode conditions under which testing of said memory cells is carried out;

    voltage switching controlling means responsive to the detection of a test mode by said test mode detecting means for switching between circuit configurations;

    voltage generating means, responsive to said voltage switching control means, for generating a first voltage lower than normal operating voltage of said memory cells and a second voltage higher than normal operating voltage of said memory cells; and

    means for applying said first and said second voltages to a corresponding bit line.

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