Redundancy removal using quasi-algebraic methods

• US 5,524,082 A
• Filed: 06/28/1991
• Issued: 06/04/1996
• Est. Priority Date: 06/28/1991
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Rosser, Thomas E., Sawkar, Prashant S., Horstmann, Paul W.
• Primary Examiner(s): Trans, Vincent N.
• Application Number:
  US07/723,121
• Time in Patent Office: 1,803 Days
• Field of Search: 364/488, 364/489, 364/490, 364/491
• US Class Current: 716/106
• CPC Class Codes: G06F 30/327 Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist

Abstract

A method is provided to remove redundancies in multi-level logic networks caused by reconverging signals at Boolean sum and product nodes. Generally, sum and product nodes which have potential redundancies are first identified. For each reconvergent signal at each of the nodes, it is determined whether it introduces redundancies using nondestructive Boolean analysis. No two-level expansion is made of the logic network. Moreover, for each confirmed redundancy, a redundant term is identified using Boolean analysis. Finally, the redundancy is removed, if desirable.

Claims

1. A computer-based method for optimizing the ultimate implementation of a logic network by identifying redundancies in signal paths caused by reconverging signals, comprising the steps of:

(a) identifying Boolean sum and product nodes in a database model of a logic network;

(b) determining whether a convergent signal exists for each of said Boolean sum and product nodes;

(c) identifying a redundant term for each of said Boolean sum and product nodes having a convergent signal; and

(d) removing said redundant term from said database model.

2. The method of claim 1, wherein step (c) comprises the step of identifiying either a maximum AND term or a maximum OR term.

3. The method of claim 1, wherein said step (b) comprises the steps of:

(i) identifying two logic inputs to one of said Boolean sum and product nodes;

(ii) identifying a leaf set for each of said two logic inputs; and

(ii) determining whether said leaf sets for said two logic inputs have any common leaves, wherein a common leaf indicates a redundancy.

4. The method of claim 3, wherein said step (c) comprises the steps of:

(i) propogating a signal from said common leaf to root pins of said sum node or said product node;

(ii) determining the signal phase of said signal; and

(iii) if said signal phase is in-phase, then determining for said product node a maximum OR term that contains said common leaf and for said sum node a maximum AND term that contains said common leaf, and if the signal phase is out-of-phase, then determining for said product node a maximum AND term that contains said common leaf and for said sum node a maximum OR term that contains said common leaf.

5. The method of claim 1, further comprising the steps of determining whether the existence of said redundant term in said model would result in said compact logic and permitting said redundant term to remain in said model if said compact logic would result.

6. The method of claim 1, further comprising the step of replicating the logic between said redundant term and the respective node with said redundant term deleted.

7. The method of claim 1, further comprising the step of replacing said redundant term with a constant logic source.

8. The method of claim 1, further comprising the step of deleting the logic block generating the redundant term.

9. The method of claim 1, wherein said logic network is an unmodified logic network.

10. A computer system having access to a computer readable medium which has computer program logic recorded thereon, said logic establishing a network configuration in accordance with a plurality of protocols of a network architecture, said computer system comprising:

first means for identifying Boolean sum and product nodes in a database model of a logic network;

means for determining whether a convergent signal exists for each of said Boolean sum and product nodes;

second means for identifying a redundant term for each of said Boolean sum and product nodes having a convergent signal; and

means for removing said redundant term from said database model.

11. The computer system of claim 10, wherein said second means for identifying comprises means for identifiying either a maximum AND term or a maximum OR term.

12. The computer system of claim 10, wherein said means for determining comprises:

means for identifying two logic inputs to one of said Boolean sum and product nodes;

means for identifying a leaf set for each of said two logic inputs; and

means for determining whether said leaf sets for said two logic inputs have any common leaves, wherein a common leaf indicates a redundancy.

13. The method of claim 12, wherein said step second means for identifying comprises:

means for propogating a signal from said common leaf to root pins of said sum node or said product node;

means for determining the signal phase of said signal;

means for determining for said product node a maximum OR term that contains said common leaf and for said sum node a maximum AND term that contains said common leaf, if said signal phase is in-phase; and

means for determining for said product node a maximum AND term that contains said common leaf and for said sum node a maximum OR term that contains said common leaf, if said signal is out-of-phase.

14. The computer system of claim 10, further comprising means for determining whether the existence of said redundant term in said model would result in said compact logic and permitting said redundant term to remain in said model if said compact logic would result.

15. The computer system of claim 10, further comprising means for replicating the logic between said redundant term and the respective node with said redundant term deleted.

16. The computer system of claim 10, further comprising means for replacing said redundant term with a constant logic source.

17. The computer system of claim 10, further comprising means for deleting the logic block generating the redundant term.

18. The computer system of claim 10, wherein said logic network is an unmodified logic network.

19. A method for removing redundancies in a logic network, comprising the steps of:

(1) building a logic model of the logic network;

(2) analyzing said logic model in order to generate a list of sum nodes and product nodes, wherein said list only contains sum nodes and product nodes that have a potential redundancy;

(3) identifying redundancies in said logic model by analyzing all pin pairs of said sum nodes and said product nodes, wherein for each pair of pins said identifying step includes,

(i) selecting a pair of pins;

(ii) identifying a leaf set for each pin in said pair of pins;

(iii) comparing said leaf sets to determine whether said leaf sets have any leaves in common, wherein a common leaf is indicative of a redundancy; and

(iv) performing a Boolean analysis on said redundancy to determine a redundant term; and

(4) removing said redundant term from said logic network.

20. The method of claim 19, wherein said step of generating said list includes only placing a sum node or a product node on said list if said sum node or said product node fan out.

21. The method of claim 19, wherein said step of performing a Boolean analysis includes the steps of:

(a) propogating a signal from said common leaf to root pins of said sum node or said product node;

(b) determining whether the signal phase of said signal is either in-phase or out-of phase at said root pins, and if the signal phase is in-phase, then determining for said product node a maximum OR term that contains said common leaf and for said sum node a maximum AND term that contains said common leaf, and if the signal phase is out-of-phase, then determining for said product node a maximum AND term that contains said common leaf and for said sum node a maximum OR term that contains said common leaf, wherein said maximum OR term or said maximum AND term is said redundant term.

22. The method of claim 21, further comprising the step of determining if a logic path from said maximum OR term or said maximum AND term to said sum node or said product node is free of any fanouts.