Method and apparatus for testing semiconductor devices at speed
First Claim
1. A method for testing semiconductor devices at operating speed, comprising the steps of:
- loading test data from a logic tester into a test data storage register;
loading the test data from the test data storage register into inputs of the semiconductor device combinational logic operating circuits;
synchronizing a semiconductor device clock with a test clock of the logic testerstarting operation of the semiconductor device combinational logic operating circuits on the test data with a first clock pulse, wherein the first clock pulse is generated from the semiconductor device clock by clock control logic;
stopping operation of the semiconductor device combinational logic operating circuits on the test data with a second clock pulse, wherein the second clock pulse is generated from the semiconductor device clock by the clock control logic,wherein the time between the first and second clock pulses is the time in which the semiconductor device combinational logic operating circuits operate; and
unloading output data generated from the operation of the semiconductor device combinational logic operating circuits on the test data.
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Abstract
A method and apparatus for testing semiconductor devices at device operating speed for both proper combinational and timing logic functions with a standard low speed logic tester. A high speed phase-lock-loop system clock of the semiconductor device is frequency and phase locked to the lower speed logic tester clock. Test data is shifted into the semiconductor device at the test clock speed. Two controlled system clock pulses are utilized to clock the test data into the semiconductor devices. The first of these two pulses starts the test and the second ends the test. In this way, the combinational functions of the semiconductor devices are tested at the system operating speed.
111 Citations
10 Claims
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1. A method for testing semiconductor devices at operating speed, comprising the steps of:
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loading test data from a logic tester into a test data storage register; loading the test data from the test data storage register into inputs of the semiconductor device combinational logic operating circuits; synchronizing a semiconductor device clock with a test clock of the logic tester starting operation of the semiconductor device combinational logic operating circuits on the test data with a first clock pulse, wherein the first clock pulse is generated from the semiconductor device clock by clock control logic; stopping operation of the semiconductor device combinational logic operating circuits on the test data with a second clock pulse, wherein the second clock pulse is generated from the semiconductor device clock by the clock control logic, wherein the time between the first and second clock pulses is the time in which the semiconductor device combinational logic operating circuits operate; and unloading output data generated from the operation of the semiconductor device combinational logic operating circuits on the test data.
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2. A method for testing semiconductor device combinational logic operating circuits at operating speed, comprising the steps of:
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loading test data from a logic tester into a test data storage register while unloading from the test data storage register the resulting test data from a prior test to the logic tester at the logic tester test clock rate during a scan input/output cycle; loading the test data from the test data storage register into inputs of the semiconductor device combinational logic operating circuits during a strobe output cycle; stabilizing the states of the loaded test data at the inputs of the semiconductor device combinational logic operating circuits during a stabilize cycle; synchronizing the frequency and phase of a phase-lock-loop oscillator with the frequency and phase of the test clock of the logic tester; starting operation of the semiconductor device combinational logic operating circuits on the test data with a first clock pulse, wherein the first clock pulse is generated from the phase-lock-loop oscillator by clock control logic during an input cycle; stopping operation of the semiconductor device combinational logic operating circuits on the test data with a second clock pulse, wherein the second clock pulse is generated from the phase-lock-loop oscillator by the clock control logic during the input cycle, wherein the time between the first and second clock pulses is the time in which the semiconductor device combinational logic operating circuits operate; and storing in the test data storage register the resulting data generated from the operation of the semiconductor device combinational logic operating circuits on the test data loaded during the strobe output cycle.
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3. A system for testing semiconductor devices at operating speed, said system comprising:
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a logic tester having a test data output, a test data input, a control output and a test clock; a semiconductor device comprising; semiconductor device combinational logic operating circuits; a phase-lock-loop oscillator having a reference input and a clock output; a clock control circuit connected between the clock output of the phase-lock-loop oscillator and the semiconductor device Combinational logic operating circuits; and test data storage circuits, the test data storage circuits connected to the semiconductor device combinational logic operating circuits; the phase-lock-loop reference input connected to the test clock of the logic tester; the phase-lock-loop being synchronized in frequency and phase to the logic tester test clock frequency; the test data storage circuits connected to the logic tester test data output and input, and receiving and transmitting test data therebetween, respectively; and the clock control circuit controlling the phase-lock-loop clock output so that first and second clock pulses thereof control operation of the semiconductor device combinational logic operating circuits; wherein the first clock pulse starts operation of the semiconductor device combinational logic operating circuits on the test data and the second clock pulse stops operation of the semiconductor device combinational logic operating circuits on the test data and the resulting data from operation thereof is stored in the test data storage logic.
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4. A semiconductor device having testing circuits for testing said semiconductor device combinational logic operating circuits at operating speed, said semiconductor device comprising:
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a phase-lock-loop oscillator having a reference input and a clock output; a clock control circuit connected between the clock output of said phase-lock-loop oscillator and the semiconductor device combinational logic operating circuits; test data storage circuits, said test data storage circuits connected to the semiconductor device combinational logic operating circuits; said phase-lock-loop oscillator reference input having a connection for connecting to a logic tester test clock; said phase-lock-loop oscillator having the capability of being synchronized in frequency and phase to the logic tester test clock frequency; said test data storage circuits having connections for connecting to the logic tester and being capable of receiving and transmitting test data therebetween; and said clock control circuit receiving the phase-lock-loop oscillator clock output and creating first and second clock pulses therefrom so as to control operation of the semiconductor device combinational logic operating circuits at speed; wherein the first clock pulse starts operation of the semiconductor device combinational logic operating circuits on the test data and the second clock pulse stops operation of the semiconductor device combinational logic operating circuits on the test data. - View Dependent Claims (5, 6, 7, 8, 9, 10)
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Specification