Microcomputer system with watchdog monitoring of plural and dependent overlapping output therefrom

• US 5,524,117 A
• Filed: 10/05/1990
• Issued: 06/04/1996
• Est. Priority Date: 03/22/1985
• Status: Expired due to Fees

• Current Assignee: Siemens AG
• Original Assignee: Siemens AG
• Inventors: Lang, Otto
• Primary Examiner(s): Harrell, Robert B.
• Application Number:
  US07/593,559
• Time in Patent Office: 2,069 Days
• Field of Search: 364/DIG. 1 MS File, 364/DIG. 2 MS File, 395/550, 395/800, 395/575, 371/16.3, 371/62
• US Class Current: 714/815
• CPC Class Codes: G06F 11/0757 by exceeding a time limit, i.e. time-out, e.g. watchdogs

Abstract

A coincidence detecting circuit is connected to multiple output lines of the microprocessor, and for resetting a microprocessor in response to a nondetection of coincidence within a predetermined period. The time sequence of pulses on one of the lines is changed by lengthening the pulses so as to coincide with signals on other channels. The operating program of the microprocessor is altered, if necessary, so as to produce signals on plural channels having predetermined time relationships with each other.

Claims

1. Apparatus for monitoring a circuit arrangement including a microprocessor, comprising a plurality of separate and independent check pulse channels, evaluation means connected to said check pulse channels, means connected to said channels for supplying, during fault-free operation of said microprocessor, check pulses of limited time duration to each of said check pulse channels in a predetermined sequence, said sequence normally causing said channels to produce a plurality of groups of pulses at different times with the check pulses on one channel being in predetermined time relationship with the check pulses on another channel of said plurality of channels, said evaluation means being connected to said channels for receiving said groups of pulses and for generating an acknowledgement signal pursuant to each group of received check pulses which has said predetermined time relationship, and including a timer circuit responsive to said acknowledgement signal and connected to said evaluation means for producing a reset output, and means connected to said reset output for resetting said microprocessor, wherein resetting of said microprocessor is prevented only when said check pulses indicate normal operation of all of said pulse channels at about the same time, wherein said evaluation means includes a pulse counter connected to receive pulses from a clock generator, and producing an output signal when said counter reaches a predetermined counting state, and means connected to said output signal for inhibiting the further counting of said counter.

2. Apparatus according to claim 1, wherein said evaluation means includes an AND gate having one input connected to a source of clock pulses and another input connected to the output of said counter, and said AND gate'"'"'s output connected to supply said reset output.

4. Apparatus according to claim 1, wherein said converter means comprising an edge-triggerable one-shot multivibrator responsive to the pulses on said one channel, whereby the pulses on said one channel are reshaped so that they are at least partially coincident with corresponding pulses on a different channel.

3. A machine executed method of monitoring operation of a circuit arrangement including a microprocessor, including the steps of normally causing, during fault-free operation of said microprocessor, two separate and independent output channels of said microprocessor to each produce pulse signals of limited time duration, and for resetting said microprocessor when said channels do not both manifest said pulse signals with the signals on one channel having a predetermined time relationship to the signals on the other channel, whereby resetting of said microprocessor is prevented only when said pulse signals on both channels indicate normal operation thereof at about the same time, including the step of altering the time duration of pulses on one of said channels so that pulses on said one channel having a predetermined time relationship with signals on the other channel are lengthened so as to overlap the signals on said other channel.

5. Apparatus for monitoring a circuit arrangement including a microprocessor, comprising a plurality of separate and independent check pulse channels, evaluation means connected to said check pulse channels, means connected to said channels for supplying, during fault-free operation of said microprocessor, check pulses of limited time duration to each of said check pulse channels in a predetermined sequence, said sequence normally causing said channels to produce a plurality of groups of pulses at different times with the check pulses on one channel being in predetermined time relationship with the check pulses on another channel of said plurality of channels, said evaluation means being connected to said channels for receiving said groups of pulses and for generating an acknowledgement signal pursuant to each group of received check pulses which has said predetermined time relationship, and including a timer circuit responsive to said acknowledgement signal and connected to said evaluation means for producing a reset output, and means connected to said reset output for resetting said microprocessor, wherein resetting of said microprocessor is prevented only when said check pulses indicate normal operation of all of said pulse channels at about the same time, wherein said supplying means includes means for producing pulses on said channels which are separated in time, and including converter means connected to one of said channels to convert pulses on said one channel into pulses which overlap the pulses on the other said channel.