Neuro-computer system for executing a plurality of controlling algorithms
First Claim
1. A neuro-computer comprising:
- a neuron array having a plurality of neurons each including at least the following elements (a) to (l),(a) a rewritable memory and a register file,(b) a memory write value holding means for holding data to be written in said rewritable memory,(c) a shifter and an ALU (Arithmetic Logic Unit),(d) a signal selecting means for selecting two values, in accordance with a control signal from a control logic unit, from at least one signal including inputs from said rewritable memory, said register, and an external circuit of said neuron, and outputs from said ALU and said shifter,(e) a select signal holding means for holding said selected two values,(f) a multiplier for multiplying the values held by said select signal holding means,(g) a multiplication result holding means for holding a multiplication result of said multiplier,(h) an operation result holding means for holding an output from said ALU or said shifter,(i) a shifter input selecting means and an ALU input selecting means for selecting inputs to said shifter and said ALU from outputs from said operation result holding means, said select signal holding means, and said multiplication result holding means,(j) a first operation result selecting means for selecting outputs from said shifter and said ALU, and determining an input to said operation result holding means,(k) a second operation result selecting means for selecting the outputs from said shifter and said ALU, and determining an output to said memory write value holding means, said register file, output selecting means for selecting an output to the external circuit of said neuron, and said signal selecting means for selecting said two values, and(l) said output selecting means for selecting an output to the external circuit of said neuron, from the outputs from said shifter, said ALU, said rewritable memory, and said register file;
a control storage unit for storing a microinstruction for controlling said neuron array;
a global memory unit for storing data necessary for information processing at said neuron array; and
said control logic unit including a means for controlling said control storage unit, a means for controlling said global memory unit, a neuron array controlling means for controlling said neuron array in accordance with said microinstruction in said control storage unit, and an external bus interface means for accessing data via an external bus.
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Abstract
A general neuro-computer and system using it is capable of executing a plurality of learning algorithms, providing an instruction execution speed comparable with a hard wired system, and practically neglecting a time required for rewriting microprograms. The neuro-computer is constituted by a neuron array having a plurality of neurons, a control storage unit for storing microinstructions, a parameter register, a control logic, and a global memory. A host computer as a user interface inputs information necessary for the learning and execution of the neuro-computer to the system, the information including learning algorithms, neural network architecture, the number of learnings, the number of input patterns, input signals, and desired signals. The information inputted from the host computer is transferred via a SCSI to the neuro-computer to perform a desired neural network operation.
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Citations
30 Claims
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1. A neuro-computer comprising:
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a neuron array having a plurality of neurons each including at least the following elements (a) to (l), (a) a rewritable memory and a register file, (b) a memory write value holding means for holding data to be written in said rewritable memory, (c) a shifter and an ALU (Arithmetic Logic Unit), (d) a signal selecting means for selecting two values, in accordance with a control signal from a control logic unit, from at least one signal including inputs from said rewritable memory, said register, and an external circuit of said neuron, and outputs from said ALU and said shifter, (e) a select signal holding means for holding said selected two values, (f) a multiplier for multiplying the values held by said select signal holding means, (g) a multiplication result holding means for holding a multiplication result of said multiplier, (h) an operation result holding means for holding an output from said ALU or said shifter, (i) a shifter input selecting means and an ALU input selecting means for selecting inputs to said shifter and said ALU from outputs from said operation result holding means, said select signal holding means, and said multiplication result holding means, (j) a first operation result selecting means for selecting outputs from said shifter and said ALU, and determining an input to said operation result holding means, (k) a second operation result selecting means for selecting the outputs from said shifter and said ALU, and determining an output to said memory write value holding means, said register file, output selecting means for selecting an output to the external circuit of said neuron, and said signal selecting means for selecting said two values, and (l) said output selecting means for selecting an output to the external circuit of said neuron, from the outputs from said shifter, said ALU, said rewritable memory, and said register file; a control storage unit for storing a microinstruction for controlling said neuron array; a global memory unit for storing data necessary for information processing at said neuron array; and said control logic unit including a means for controlling said control storage unit, a means for controlling said global memory unit, a neuron array controlling means for controlling said neuron array in accordance with said microinstruction in said control storage unit, and an external bus interface means for accessing data via an external bus. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21)
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22. A neuro-computer system comprising:
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a neuro-computer processing information by using at least one type of a neural network, said neuro-computer including a neuron array comprising at least one neuron, a control storage unit for storing a microinstruction for controlling said neuron array, a global storage unit for storing data necessary for processing information by using said neuron array, a parameter storage unit for storing parameter information including the number of learnings and the number of input patterns, and a control logic unit for controlling said control storage unit, said global storage unit, and said parameter storage unit by using said microinstruction, said parameter information, and data necessary for a neural network operation; a host computer for controlling at least a start and stop of said neuro-computer and inputting necessary information for the learning and execution of said neuro-computer to said neuro-computer, said necessary information including a learning algorithm, a neural network architecture, a number of learnings, a number of input patterns, an input signal, and a desired signal (an expected value); and a means for interconnecting said neuro-computer and said host computer, wherein said neuron of said neuro-computer includes; a logic circuit for realizing a neural network operation; a condition code register for indicating an operation result of said logic circuit; a group register for holding the value of said condition code register and an inverted value of said value and for controlling the operation and grouping of said neuron; a neuron request register for holding the value of said condition code register and an inverted value of said value and for supplying said control logic unit with the state of said neuron; a means for storing, when executing the neural network operation by using a weight value, an output value, and a back propagation error, respectively of a predetermined number of bits, a weight value having a number of bits greater than said predetermined number of bits; a means for reading and operating a weight value of a predetermined number of bits from said weight value storing means when calculating a neuron output value and a back propagation error during the operation; and a means for reading and operating a weight value having the number of bits greater than said predetermined number of bits when modifying the weight value during the operation, said control logic unit of said neuro-computer comprising; a means for controlling said control storage means; a means, having an address translation table for generating a neuron address and a logic circuit for detecting the maximum and minimum values of neuron output values, for controlling said neuron array in accordance with said microinstruction read from said control storage unit; a means for controlling said global memory unit and said parameter storage unit; and an external bus interface means for accessing data via an external bus, said neuro-computer comprising; a first pipeline latch provided on a bus of said neuro-computer; a second pipeline latch for transferring data from said neuron to another neuron after said microinstruction is issued, said second pipeline latch having a number of stages equal to a number of stages of a pipeline latch for transferring data from said global storage unit to said neuron after said microinstruction is issued; a register for saving data left in said first and second pipeline latches when the neural network operation is intercepted; and a means for sequentially outputting said saved data when executing again said intercepted operation, and said host computer comprising; a means for generating said microinstruction describing the neural network operation from network definition information including the number of layers of the neural network and the number of neurons at each layer; a time sequential data receiving means for periodically receiving time sequential data via a communication line; a data converting means for converting said received time sequential data into a data format capable of being processed by said neuro-computer; a data transmitting/receiving means for transferring said converted data to said neuro-computer, and receiving data transferred from said neuro-computer; and a display and processing means for processing and displaying the data received by said data transmitting/receiving means. - View Dependent Claims (23)
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24. A neuro-computer system comprising:
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a neuro-simulator for realizing a neural network operation by using software; a neuro-computer for realizing the neural network operation by using hardware; a neuro-learning information generating means for generating neuro-learning information necessary for neural network learning; a data switching information storage means for storing reference information used for a judgement of switching between said software and said hardware; and a data switching means for switching said neuro-learning information in accordance with said reference information. - View Dependent Claims (25, 26, 27, 28, 29, 30)
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Specification