Multiprocessor system with write generate method for updating cache
First Claim
1. A method for updating cache memory in a multiprocessor system having shared memory, comprising the steps of:
- allocating a first area of shared memory as being for data that is written before being read, and indicating at one of line or page units of shared memory that a given unit is write before read;
implementing a write operation of data through cache memory for a shared memory address within the write before read area by (1) updating a tag for a first line of the cache memory corresponding to said shared memory address without reading from shared memory, (2) writing said data to a corresponding portion of said first line irrespective of whether said data is a byte, word, or double word and irrespective of whether said data is word-aligned in the first line, (3) setting a third status for said first line denoting valid data is present; and
(4) setting a second status for said first line denoting that the first line has been write generated; and
checking said second status during a later write operation to said first line to determine whether to treat the later write operation as a cache miss.
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Abstract
A plurality of program processors, shared memory, dual port memory, external cache memory and a control processor form a multiprocessor system. A shared memory bus links the program processors, shared memory, dual port memory and external cache memory. Program processor I/O occurs through a pair of serial I/O channels coupled to one port of the dual port memory. A write generate mode is implemented for updating cache by first allocating lines of shared memory as write before read areas. For such lines, cache tags are updated directly on cache misses without reading from memory. A hit is forced for such line, resulting in valid data at the updated part and invalid data at the remaining portion. Thus, part of the line is written to and the rest invalidated. The invalid portions are not read, unless preceded by a write operation. The mode reduces the number of bus cycles by making write misses more efficient.
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Citations
6 Claims
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1. A method for updating cache memory in a multiprocessor system having shared memory, comprising the steps of:
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allocating a first area of shared memory as being for data that is written before being read, and indicating at one of line or page units of shared memory that a given unit is write before read; implementing a write operation of data through cache memory for a shared memory address within the write before read area by (1) updating a tag for a first line of the cache memory corresponding to said shared memory address without reading from shared memory, (2) writing said data to a corresponding portion of said first line irrespective of whether said data is a byte, word, or double word and irrespective of whether said data is word-aligned in the first line, (3) setting a third status for said first line denoting valid data is present; and
(4) setting a second status for said first line denoting that the first line has been write generated; andchecking said second status during a later write operation to said first line to determine whether to treat the later write operation as a cache miss. - View Dependent Claims (2, 3, 4)
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5. A multiprocessor system having a single-board processor cluster, the cluster comprising:
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a plurality of program processors; shared memory accessible by each one of said plurality of program processors via a shared memory bus; dual port memory coupled to the shared memory bus and having a first port and a second port; a pair of serial I/O channels accessible by each one of said plurality of program processors via said dual port memory, a first I/O channel of said pair for receiving first data from outside the cluster and a second I/O channel of said pair for outputting second data received from within the cluster; wherein the first port of dual port memory is coupled to the pair of I/O channels and the second port is coupled to the shared memory bus; a control processor for (1) scheduling processing tasks among program processors, (2) managing time-shared I/O operations to and from respective program processors across the pair of serial I/O channels, and (3) managing communication between program processors; and external cache memory coupled to the shared memory bus, in which a first area of shared memory is allocated as being for data that is written before being read, the first area allocated in one of line or page units of shared memory, a first status associated with each unit indicating whether unit is write before read; the external cache memory having a cache write generate mode during which a write generate operation specifying an address in the first area is validated on a cache-write miss without reading data from shared memory, the write generate operation comprising;
(1) updating a tag for a first line of the cache memory corresponding to said first area address without reading from shared memory, (2) writing said data to a corresponding portion of said first line irrespective of whether said data is a byte, word, or double word and irrespective of whether said data is word-aligned in the cache memory line, (3) setting a third status for said first line denoting valid data is present; and
(4) setting a second status for said first line denoting that the first line includes dirty data; and
in which said second status is checked during a later write operation to said first line to determine whether to treat the later write operation as a cache miss. - View Dependent Claims (6)
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Specification