Bus protocol and method for controlling a data processor

• US 5,524,215 A
• Filed: 10/05/1993
• Issued: 06/04/1996
• Est. Priority Date: 10/05/1993
• Status: Expired due to Term

• Current Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Gay, James G.
• Primary Examiner(s): Ray, Gopal C.
• Application Number:
  US08/133,413
• Time in Patent Office: 973 Days
• Field of Search: 395/325, 395/725, 395/275, 395/425, 395/287, 395/288, 395/293, 395/200.01, 395/800, 370/85.2, 370/85.6, 340/825.5, 340/825.52
• US Class Current: 710/107
• CPC Class Codes: G06F 13/364 using independent requests or grants, e.g. using separated request and grant lines
• CPC Class Codes: G06F 13/4213 with asynchronous protocol

Abstract

A bus protocol uses signals to designate a bus transfer termination (BTT*) and a bus grant relinquish (BGR*). The BTT* signal is an output which is asserted by a bus master which currently has ownership of a bus to indicate to other potential bus masters that a bus transfer is complete and that bus ownership may be transferred to another bus master. The BGR* signal is an input to a bus master. When BGR* is asserted, a bus arbiter/controller is informing the current bus master that the bus must be relinquished as soon as possible, after the deassertion of the Bus Grant signal, with no regard for locked sequences. If BGR* is deasserted, the bus arbiter is informing the current bus master that the bus can be relinquished at a time which is convenient for the current bus master. In general, BGR* is a bit which indicates the urgency of a pending bus ownership transfer.

Claims

1. A microprocessor implemented bus protocol method for controlling a bus transfer with a bus controller, the method comprising the steps of:

granting bus ownership to a master circuit by asserting a first control signal from a bus controller wherein the granting is conditioned only on the first control signal;

transferring data between the master circuit and a device external to the master circuit in response to the assertion of a second control signal which indicates that the bus transfer is to initiated;

sending a third control signal from the bus controller to the master circuit wherein the third control signal indicates to the master circuit whether the master circuit bus ownership should be relinquished at the termination of a current bus cycle when the first control signal is deasserted or should be terminated at the discretion of the master circuit when the first control signal is deasserted;

deasserting the first control signal to indicate to the master circuit that the bus ownership should be relinquished;

relinquishing the bus ownership at either the termination of the current bus cycle or at the discretion of the master circuit as determined by the third control signal; and

communicating external to the master circuit that the master circuit has terminated its bus ownership by asserting a fourth control signal wherein the fourth control signal is asserted by the master circuit, the fourth control signal being asserted at a time which is determined by the state of the third control signal and the first control signal, the fourth control signal being tri-stated during bus ownership by the master circuit, being tri-stated during lack of bus ownership by the master circuit, and only being asserted when bus ownership is being transitioned between a granted state and an ungranted state with respect to the master circuit.

2. The bus protocol method of claim 1 wherein the step of communicating external to the master circuit that the master circuit has terminated its bus ownership by asserting the fourth control signal comprises the steps of:

driving the fourth control signal to a logic zero value for only a single first clock cycle of the master circuit; and

driving the fourth control signal to a logic one value for only a single second clock cycle wherein the second clock cycle directly follows the first clock cycle in time.

3. The bus protocol method of claim 1 wherein the step of communicating external to the master circuit that the master circuit has terminated its bus ownership by asserting the fourth control signal comprises the steps of:

driving the fourth control signal to a first logic value from a tri-state value wherein the first logic value is maintained only for one clock cycle;

driving the fourth control signal to a second logic value from the first logic value wherein the second logic value is different from the first logic value and the second logic value being maintained for only one clock cycle; and

driving the second logic value to the tri-state value.

4. The bus protocol method of claim 1 wherein the step of sending the third control signal to the master circuit comprises:

indicating to the master circuit that a locked sequence of bus transfers must be prematurely terminated due to a logic state of the third control signal.

5. A data processing system having a bus protocol for allowing a first circuit to interface to a second circuit through a bus, the data processing system comprising:

circuitry for providing a first control signal as an output from the first circuit to indicate that ownership of the bus is requested;

circuitry for receiving a second control signal as an input to the first circuit which is used to indicate whether the first circuit is granted ownership of the bus; and

circuitry for providing a third control signal as an output from the first circuit wherein the third control signal is asserted only when the first circuit is ready to relinquish ownership of the bus, the third control signal being tri-stated during a first time period when the first circuit has control of the bus, being tri-stated during a second time period when the first circuit lacks control of the bus and being asserted to both a high voltage and a low voltage in a time sequential and mutually exclusive manner in two clock cycle time period when transitioning in time from the first time period to the second time period.

6. The data processing system of claim 5 wherein the third control signal is provided as an input/output signal wherein the third control signal can be driven by the first circuit in a first time interval and read by the first circuit in a second time interval.

7. The data processing system of claim 6 wherein the third control signal is read by the first circuit in order to determine when the bus is available for use.

8. The data processing system of claim 5 further comprising:

means for providing a fourth control signal as an output of the first circuit wherein the fourth control signal indicates, external to the first circuit, the start of a bus cycle.

9. The data processing system of claim 8 further comprising:

means for recording past assertions of the fourth control signal and the third control signal in order to determine when in time the bus is available for ownership use.

10. The data processing system of claim 5 wherein a bus arbiter circuit determines whether the first circuit within the system is given mastership of the bus.

11. A microprocessor implemented bus protocol for allowing a first circuit to interface to a second circuit through a bus, the bus protocol comprising:

means for providing a first control signal as an output from the first circuit to indicate that ownership of the bus is requested;

means for receiving a second control signal as an input to the first circuit which is used to indicate whether the first circuit is granted ownership of the bus; and

means for receiving a third control signal as an input to the first circuit wherein the third control signal is set to a first logic state to indicate that the first circuit must relinquish bus ownership in response to deassertion of the first control signal at the end of a current bus cycle being performed by the first circuit when the deassertion of the first control signal occurs and wherein the third control signal is set to a second logic state to indicate that the first circuit is to relinquish bus ownership in response to deassertion of the first control signal at a convenient time determined by the first circuit when the deassertion of the first control signal occurs.

12. The bus protocol of claim 11 further comprising:

means for providing a fourth control signal as an output of the first circuit wherein the fourth control signal indicates, external to the first circuit, the start of a bus cycle.

13. The bus protocol of claim 12 further comprising:

means for keeping track of past assertions of the fourth control signal in order to determine when in time the bus is available for ownership use.

14. The method of claim 11 wherein a bus arbiter circuit, coupled to the first circuit, generates the second control signal.

15. The bus protocol of claim 11 wherein the third control signal to the master circuit is used to indicate to the master circuit that a locked sequence of bus transfers must be prematurely terminated due to the state of the third control signal.

16. The bus protocol of claim 11 wherein the assertion of the third control signal indicates to the first circuit that the first circuit must relinquish bus ownership at the end of a current bus cycle being performed by the first circuit and deassertion of the third control signal indicates to the first circuit that the first circuit is to relinquish bus ownership at a convenient time after deassertion of the second control signal, the convenient time being determined by the first circuit.

17. A microprocessor implemented bus protocol for allowing a first circuit to interface to a second circuit through a bus, the bus protocol comprising:

means for providing a first control signal as an output from the first circuit to indicate that ownership of the bus is requested;

means for receiving a second control signal as an input to the first circuit which is used to indicate whether the first circuit is granted ownership of the bus;

means for receiving a third control signal as an input to the first circuit wherein the third control signal is set to a first logic state to indicate that the first circuit must relinquish bus ownership at the end of a current bus cycle being performed by the first circuit and wherein the third control signal is set to a second logic state to indicate that the first circuit is to relinquish bus ownership at a convenient time determined by the first circuit; and

means for providing a fourth control signal as an output from the first circuit wherein the fourth control signal is asserted only when the first circuit is ready to relinquish ownership of the bus, the fourth control signal being tri-stated during a first time period when the first circuit has control of the bus, being tri-stated during a second time period when the first circuit lacks control of the bus, and being asserted to both a high voltage and a low voltage in a time sequential and mutually exclusive manner in a two clock cycle time period when transitioning in time from the first time period to the second time period.

18. The bus protocol of claim 17 wherein the fourth control signal is provided as an input/output signal wherein the fourth control signal can be driven by the first circuit in a first time interval and read by the first circuit in a second time interval.

19. The bus protocol of claim 18 wherein the fourth control signal is read by the first circuit in order to determine when the bus is available for use.

20. The bus protocol of claim 17 further comprising:

means for providing a fifth control signal as an output of the first circuit wherein the fifth control signal indicates, external to the first circuit, the start of a bus cycle.

21. The bus protocol of claim 20 further comprising:

means for keeping track of past assertions of the fifth control signal and the fourth control signal in order to determine when in time the bus is available for ownership use.

22. The bus protocol of claim 17 wherein a bus arbiter circuit, coupled to the first circuit, generates the second control signal.

23. The bus protocol of claim 17 wherein third control signal to the master circuit is used to indicate to the master circuit that a locked sequence of bus transfers must be prematurely terminated due to the state of the third control signal.

24. The bus protocol of claim 17 wherein the assertion of the third control signal indicates to the first circuit that the first circuit must relinquish bus ownership at the end of a current bus cycle being performed by the first circuit and deassertion of the third control signal indicates to the first circuit that the first circuit is to relinquish bus ownership at a convenient time after deassertion of the second control signal, the convenient time being determined by the first circuit.

25. A microprocessor implemented bus protocol method for allowing a first circuit to interface to a second circuit through a bus, the bus protocol method comprising the steps of:

providing a first control signal out from the first circuit to indicate that the first circuit is requesting ownership of the bus;

providing a second control signal into the first circuit which is used to indicate whether the first circuit is granted ownership of the bus; and

providing a third control signal into the first circuit wherein the third control signal is set to a first logic state to indicate that the first circuit must relinquish bus ownership at the end of a current bus cycle being performed by the first circuit and wherein the third control signal is set to a second logic state to indicate that the first circuit is to relinquish bus ownership at any time which is subsequent to deassertion of the second control signal, said time being a convenient time determined by the first circuit, the first control signal only performing bus granting functions where the first control signal is not used to communicate information identical to the third control signal.