Coherency for write-back cache in a system designed for write-through cache including write-back latency control

• US 5,524,234 A
• Filed: 12/28/1994
• Issued: 06/04/1996
• Est. Priority Date: 11/13/1992
• Status: Expired due to Term

• Current Assignee: VIA-Cyrix, Inc.
• Original Assignee: Cyrix Corp (Texas Instruments, Inc.)
• Inventors: Duschatko, Douglas E., Bluhm, Mark, Garibay, Raul A. Jr., Herubin, Margaret R., Courtright, David A., Byrne, Jeffrey S., Martinez, Marvin W. Jr.
• Primary Examiner(s): Moore, David K.
• Assistant Examiner(s): Whitfield, Michael A.
• Application Number:
  US08/365,972
• Time in Patent Office: 524 Days
• Field of Search: 395/425, 395/468, 395/469, 395/470
• US Class Current: 711/141
• CPC Class Codes: G06F 12/0804 with main memory updating G06F12/0806 takes precedence
• CPC Class Codes: G06F 12/0808 with cache invalidating means G06F12/0815 takes precedence
• CPC Class Codes: G06F 12/0831 using a bus scheme, e.g. with bus monitoring or watching means
• CPC Class Codes: G06F 12/0835 for main memory peripheral accesses (e.g. I/O or DMA)

Abstract

A write-back coherency system is used, in an exemplary embodiment, to implement write-back caching in an x86 processor installed in a multi-master computer system that does not support a write-back protocol for maintaining coherency between an internal cache and main memory during DMA operations. The write-back coherency system interrupts the normal bus arbitration operation to allow export of dirty data, and includes an X%DIRTY latency-control function. In response to an arbitration-request (such as HOLD), if the internal cache contains dirty data, the processor is inhibited from providing arbitration-acknowledge (such as HLDA) until the dirty data is exported (the cache is dynamically switched to write-through mode to prevent data in the cache from being made dirty while the bus is arbitrated away). While the requesting bus master is accessing memory, bus snooping is performed and invalidation logic invalidates at least those cache locations corresponding to locations in memory that are affected by the requesting bus master. The X%DIRTY function provides write-back latency control by dynamically switching the cache from write-back to write-through mode if a cache write would cause the number of cache locations containing dirty data to exceed a predetermined maximum percentage of the total number of cache locations.

Claims

1. In a multi-master computer system including a processor with an internal cache, where the computer system does not support operating the processor in write-back mode by implementing a write-back coherency protocol to maintain coherency between the internal cache and main memory during DMA (direct memory access) operations, a write-back coherency system to support use of a processor in which the internal cache is operable in write-back mode or write-through mode, comprising:

(a) cache control means for selectively switching the internal cache between write-through and write-back mode;

(b) bus arbitration means for detecting an arbitration-request signal indicating a request by a requesting bus master for a DMA operation;

(c) write-back coherency means for inhibiting, if the internal cache is in write-back mode, and if the internal cache contains dirty data, the bus arbitration logic from asserting an arbitration-acknowledge signal to allow the DMA operation to proceed until an export operation is performed to export such dirty data; and

(d) X% DIRTY means for causing the cache control logic to switch the cache from write-back to write-through mode if a write to the internal cache would cause the number of cache locations containing dirty data to exceed a predetermined maximum percentage of the total number of cache locations.

2. The write-back coherency system of claim 1, further comprising:

(a) snooping means for monitoring, during DMA operations, addresses output from the requesting bus master, and in response to each bus master address, determining whether such address corresponds to data in the cache, and if so,

(b) causing the cache control logic to perform an invalidation operation to invalidate at least the location in the cache containing such data.

3. The write-back coherency system of claim 1, wherein, after an export operation is performed, the cache control means switches the internal cache to write-through mode such that data in the cache is not made dirty while the requesting bus master has access to memory.

4. The write-back coherency system of claim 1, wherein the write-back coherency means further comprises:

PDIRTY means for indicating when the cache does not contain dirty data, such that, in response to an arbitration-request signal, if the PDIRTY means indicates that the cache does not contain dirty data, then the bus arbitration means is enabled to assert an arbitration-acknowledge signal without the internal cache being accessed to determine if it contains dirty data.

5. The write-back coherency system of claim 1, whereto the X%DIRTY means comprises:

a CDIRTYMAX register for storing a predetermined value corresponding to the maximum number of allowable cache locations containing dirty data;

a CDIRTYCUR register for storing a value corresponding to the current number of cache locations containing dirty data; and

CDIRTYCUR means for either incrementing the CDIRTYCUR value if a cache access writes to a clean-data location such that it becomes dirty, or decrementing the CDIRTYCUR value if a cache access either replaces a dirty location with new data, or invalidates or exports a dirty location.

6. In a multi-master computer system including a processor with an internal cache, where the computer system does not support operating the processor in write-back mode by implementing a write-back coherency protocol to maintain coherency between the internal cache and main memory during DMA (direct memory access) operations, a write-back coherency system to support use of a processor in which the internal cache is operable in write-back mode or write-through mode, comprising:

(a) cache control logic that selectively switches the internal cache between write-through and write-back mode;

(b) bus arbitration logic that detects an arbitration-request signal indicating a request by a requesting bus master for a DMA operation; and

(c) write-back coherency logic that, if the internal cache is in write-back mode, and if the internal cache contains dirty data, inhibits the bus arbitration logic from asserting an arbitration-acknowledge signal to allow the DMA operation to proceed until an export operation is performed to export such dirty data; and

(d) X% DIRTY logic that causes the cache control logic to switch the cache from write-back to write-through mode if a write to the internal cache would cause the number of cache locations containing dirty data to exceed a predetermined maximum percentage of the total number of cache locations.

7. The write-back coherency system of claim 6, further comprising:

(a) snooping logic that, during DMA operations, monitors addresses output from the requesting bus master, and in response to each bus master address, determines whether such address corresponds to data in the cache, and if so,

(b) causes the cache control logic to perform an invalidation operation to invalidate at least the location in the cache containing such data.

8. The write-back coherency system of claim 6, wherein, after an export operation is performed, the cache control logic switches the internal cache to write-through mode such that data in the cache is not made dirty while the requesting bus master has access to memory.

9. The write-back coherency system of claim 6, wherein the write-back coherency logic further comprises:

PDIRTY logic for indicating when the cache does not contain dirty data, such that, in response to an arbitration-request signal, if the PDIRTY logic indicates that the cache does not contain dirty data, then the bus arbitration logic is enabled to assert the arbitration-acknowledge signal without the internal cache being accessed to determine if it contains dirty data.

10. The write-back coherency system of claim 6, wherein the X%DIRTY logic comprises:

a CDIRTYMAX register for storing a predetermined value corresponding to the maximum number of allowable cache locations containing dirty data;

a CDIRTYCUR register for storing a value corresponding to the current number of cache locations containing dirty data; and

CDIRTYCUR logic for either incrementing the CDIRTYCUR value if a cache access writes to a clean-data location such that it becomes dirty, or decrementing the CDIRTYCUR value if a cache access either replaces a dirty location with new data, or invalidates or exports a dirty location.

11. A write-back coherency method for a multi-master computer system including a processor with an internal cache, where the computer system does not support operating the processor in write-back mode by implementing a write-back coherency protocol to maintain coherency between the internal cache and main memory during DMA (direct memory access) operations, the write-back coherency method supporting use of a processor in which the internal cache is operable in write-back mode or write-through mode, comprising the steps:

(a) detecting an arbitration-request signal indicating a request by a requesting bus master for a DMA operation;

(b) if the internal cache is in write-back mode, and if the internal cache contains dirty data, inhibiting the assertion of an arbitration-acknowledge signal to allow the DMA operation to proceed until an export operation is performed to export such dirty data; and

(c) if the internal cache is in write-back mode, selectively switching the internal cache to write-through mode if a write to the internal cache would cause the number of cache locations containing dirty data to exceed a predetermined maximum percentage of the total number of cache locations.

12. The write-back coherency method of claim 11, further comprising the steps of:

(a) during DMA operations, monitoring addresses output from the requesting bus master, and in response to each bus master address, determining whether such address corresponds to data in the cache, and if so,

(b) performing an invalidation operation to invalidate at least the location in the cache containing such data.

13. The write-back coherency method of claim 11, further comprising the step of:

after an export operation is performed, switching the internal cache to write-through mode such that data in the cache is not made dirty while the requesting bus master has access to memory.