System for arbitrating access to memory with dynamic priority assignment

• US 5,524,235 A
• Filed: 10/14/1994
• Issued: 06/04/1996
• Est. Priority Date: 10/14/1994
• Status: Expired due to Term

• Current Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Original Assignee: Compaq Computer Corporation (HP Inc.)
• Inventors: Collins, Michael J., Moriarty, Michael, Larson, John E., Thome, Gary W.
• Primary Examiner(s): Swann, Tod R.
• Assistant Examiner(s): O NEILL, DAVID J
• Application Number:
  US08/324,011
• Time in Patent Office: 599 Days
• Field of Search: 395/478, 395/296, 395/293, 395/728, 395/731, 395/732
• US Class Current: 711/151
• CPC Class Codes: G06F 13/1605 based on arbitration arbitration in handling access to a common bus or bus system G06F13/36
• CPC Class Codes: G06F 13/18 based on priority control G06F13/1605 takes precedence

Abstract

An arbiter circuit for controlling access to the main memory for requests asserted by the microprocessor, the refresh controller and PCI bus masters. Generally, the priority of the memory requests are as follows, with some exceptions: (1) second refresh request; (2) processor-to-memory write request; (3) memory-to-processor read request; (4) PCI-to-memory write request; (5) memory-to-PCI read request; and (6) first refresh request. The second refresh request indicates that two refreshes are outstanding. When that occurs, both outstanding refresh requests are assigned the highest priority. The processor-to-memory write request is always higher in priority than other memory requests except the second refresh. However, under certain conditions, the processor-to-memory write requests is held off to allow other cycles to proceed. The memory-to-processor read request is generally higher in priority than the PCI write and read requests, unless certain conditions occur to override that priority. PCI-to-memory write requests are always higher in priority than memory-to-PCI read requests.

Claims

1. A circuit for arbitrating access to a memory in a computer system, the computer system including a first bus, a second bus, a microprocessor coupled to the first bus, and a peripheral device coupled to the second bus, wherein the microprocessor is capable of generating write and read requests to the memory, each of the microprocessor write and read requests being provided with a first bus address, and wherein the peripheral device is capable of generating write and read requests to the memory, each of the peripheral device write and read requests being provided with a second bus address, the circuit comprising:

first receiving means coupled to the first bus for receiving microprocessor generated write and read requests;

second receiving means coupled to the second bus for receiving peripheral device generated write and read requests;

means for asserting an arbitration signal to indicate that an arbitration cycle is enabled;

means responsive to said arbitration signal and coupled to said first and second receiving means for assigning priority to said received microprocessor write and read requests and said received peripheral device write and read requests if said arbitration signal is asserted, wherein a received microprocessor write request is assigned a higher priority than a received microprocessor read request or a peripheral device write or read request, and wherein a received microprocessor read request is assigned a lower priority than a received microprocessor write request but a higher priority than a received peripheral device write request, except that a received microprocessor read request is forced lower in priority than a received peripheral device write request if;

(a) the first bus address provided with said received microprocessor read request is the same as the second bus address provided with said received peripheral device write request;

or

(b) a peripheral device read request is received while said received peripheral device write request is pending; and

means coupled to the memory and to said priority assigning means for granting access to the memory to the highest priority request.

2. The circuit of claim 1, wherein a received microprocessor read request is assigned a higher priority than a received peripheral device read request, except that a received microprocessor read request is forced lower in priority than a received peripheral device read request if (c) said received peripheral device read request is received while a peripheral device write request is pending.

3. The circuit of claim 2, wherein a currently received microprocessor read request is forced lower in priority than a received peripheral device read request if (d) said received peripheral device read request was received in a previous arbitration cycle along with a microprocessor read request and said previously received microprocessor read request was assigned the highest priority in said previous arbitration cycle.

4. The circuit of claim 3, wherein the microprocessor is capable of generating a pseudo locked read request, and wherein even if condition (c) or (d) is true, said received pseudo locked microprocessor read request is assigned a higher priority than said received peripheral read request.

5. The circuit of claim 1, wherein the microprocessor is capable of generating a locked read request, the circuit further comprising:

means coupled to the first bus for detecting said microprocessor locked read request; and

means coupled to said detecting means and to said first receiving means for asserting a lock signal if said microprocessor locked read request is detected and a peripheral device write request is not received, wherein if said lock signal is asserted, a received microprocessor locked read request is assigned a higher priority than a received peripheral write request.

6. The circuit of claim 5, wherein if said lock signal is not asserted, said received microprocessor locked read request is forced lower in priority than a received peripheral device write request.

7. The circuit of claim 1, wherein the computer system further includes a refresh controller coupled to the memory for generating a first refresh request to refresh the memory at predetermined time intervals, wherein a received first refresh request is assigned a lower priority than a received microprocessor write or read request or a received peripheral device write or read request.

8. The circuit of claim 7, wherein said refresh controller generates a second refresh request after said predetermined time interval has expired and said first refresh request has not been granted access to the memory, and wherein said second refresh request is assigned a higher priority than a received microprocessor write or read request or a received peripheral device write or read request.

9. The circuit of claim 8, wherein if a second refresh request is received, said received first refresh request is also assigned a higher priority than a microprocessor write or read request or a received peripheral write or read request.

10. The circuit of claim 1, further comprising:

a first queue coupled to said first receiving means and having a plurality of entries for storing received microprocessor write requests, wherein said priority assigning means assigns priority to received microprocessor write requests only if stored in said first queue;

a second queue coupled to said second receiving means and having a plurality of entries for storing received peripheral device write requests, wherein said priority assigning means assigns priority to received peripheral device write requests only if stored in said second queue; and

means coupled to said first and second receiving means and to said first and second queues for providing a first nopost signal, wherein said first nopost signal is asserted if said second queue is full, and wherein assertion of said first nopost signal prevents subsequently received microprocessor write requests from entering said first queue.

11. The circuit of claim 10, wherein said first nopost signal is also asserted if said first queue is not empty, said second queue is not empty, and a peripheral device read request is received.

12. The circuit of claim 10, further comprising:

means responsive to said arbitration signal and coupled to said first and second receiving means for providing a second nopost signal, wherein said second nopost signal is asserted if said arbitration signal is asserted, a microprocessor read request is received, and in a previous arbitration cycle, a microprocessor read request was forced lower in priority than a peripheral device write request because the first bus address provided with said received microprocessor read request is the same as the second bus address provided with said received peripheral device write request, and wherein asserting said second nopost signal prevents subsequently received peripheral device read requests from entering said second queue.

13. A method of arbitrating access to a memory in a computer system, the computer system including a first bus, a second bus, a microprocessor coupled to the first bus, and a peripheral device coupled to the second bus, wherein the microprocessor is capable of generating write and read requests to the memory, each of the microprocessor write and read requests being provided with a first bus address, and wherein the peripheral device is capable of generating write and read requests to the memory, each of the peripheral device write and read requests being provided with a second bus address, the method comprising the steps of:

receiving microprocessor generated write and read requests;

receiving peripheral device generated write and read requests;

asserting an arbitration signal to indicate that an arbitration cycle is enabled;

assigning priority to said received microprocessor write and read requests and said received peripheral device write and read requests if said arbitration signal is asserted, wherein a received microprocessor write request is assigned a higher priority than a received microprocessor read request or a peripheral device write or read request, and wherein a received microprocessor read request is assigned a lower priority than a received microprocessor write request but a higher priority than a received peripheral device write request, except that a received microprocessor read request is forced lower in priority than a received peripheral device write request if;

(a) the first bus address provided with said received microprocessor read request is the same as the second bus address provided with said received peripheral device write request;

or

(b) a peripheral device read request is received while said received peripheral device write request is pending; and

granting access to the memory to the highest priority request.

14. The method of claim 13, wherein a received microprocessor read request is assigned a higher priority than a received peripheral device read request, except that a received microprocessor read request is forced lower in priority than a received peripheral device read request if (c) said received peripheral device read request is received while a peripheral device write request is pending.

15. The method of claim 14, wherein a currently received microprocessor read request is forced lower in priority than a received peripheral device read request if (d) said received peripheral device read request was received in a previous arbitration cycle along with a microprocessor read request and said previously received microprocessor read request was assigned the highest priority in said previous arbitration cycle.

16. The method of claim 15, wherein the microprocessor is capable of generating a pseudo locked read request, and wherein a received pseudo locked microprocessor read request is assigned a higher priority than said received peripheral write request even if condition (c) or (d) is true.

17. The method of claim 13, wherein the microprocessor is capable of generating a locked read request, the method further comprising the steps of:

detecting for said microprocessor locked read request; and

asserting a lock signal if said microprocessor locked read request is detected and a peripheral device write request is not received, wherein if said lock signal is asserted, a received microprocessor locked read request is assigned a higher priority than a received peripheral read request.

18. The method of claim 17, wherein if said lock signal is not asserted, said received microprocessor locked read request is forced lower in priority than a received peripheral device write request.

19. The method of claim 13, wherein the computer system further includes a refresh controller coupled to the memory for generating a first refresh request to refresh the memory at predetermined time intervals, wherein a received first refresh request is assigned a lower priority than a received microprocessor write or read request or a received peripheral device write or read request.

20. The method of claim 19, wherein said refresh controller generates a second refresh request after said predetermined time interval has expired and said first refresh request has not been granted access to the memory, and wherein said second refresh request is assigned a higher priority than a received microprocessor write or read request or a received peripheral device write or read request.

21. The method of claim 20, wherein if a second refresh request is received, said received first refresh request is also assigned a higher priority than a microprocessor write or read request or a received peripheral write or read request.

22. The method of claim 13, wherein the computer system further includes a first queue having a plurality of entries for storing received microprocessor write requests and a second queue having a plurality of entries for storing received peripheral device write requests, wherein priority is assigned to received microprocessor write requests only if stored in said first queue, wherein priority is assigned to received peripheral device write requests only if stored in said second queue, the method further comprising the step of:

asserting a first nopost signal if said second queue is full, wherein asserting said first nopost signal prevents subsequently received microprocessor write requests from entering said first queue.

23. The method of claim 22, wherein said first nopost signal is also asserted if said first queue is not empty, said second queue is not empty, and a peripheral device read request is received.

24. The method of claim 22, further comprising the step of:

asserting a second nopost signal if said arbitration signal is asserted, a microprocessor read request is received, and in a previous arbitration cycle, a microprocessor read request was forced lower in priority than a peripheral device write request because the first bus address provided with said received microprocessor read request is the same as the second bus address provided with said received peripheral device write request, and wherein asserting said second nopost signal prevents subsequently received peripheral device read requests from entering said second queue.