System for dividing processing tasks into signal processor and decision-making microprocessor interfacing therewith

• US 5,524,244 A
• Filed: 02/15/1994
• Issued: 06/04/1996
• Est. Priority Date: 07/11/1988
• Status: Expired due to Term

• Current Assignee: Logic Devices Incorporated
• Original Assignee: Logic Devices Incorporated
• Inventors: Krassowski, Andrew J., Montlick, Terry F., Robinson, Jeffrey I., Rouse, Keith
• Primary Examiner(s): Kriess, Kevin A.
• Application Number:
  US08/196,389
• Time in Patent Office: 840 Days
• Field of Search: 395/700, 395/650, 364/DIG. 1, 364/280.4
• US Class Current: 717/140
• CPC Class Codes: F02B 2075/025 two
• CPC Class Codes: G06F 11/3648 using additional hardware
• CPC Class Codes: G06F 11/3664 Environments for testing or debugging software
• CPC Class Codes: G06F 13/28 using burst mode transfer, e.g. direct memory access DMA, cycle steal G06F13/32 takes precedence
• CPC Class Codes: G06F 15/173 using an interconnection network, e.g. matrix, shuffle, pyramid, star, snowflake
• CPC Class Codes: G06F 15/177 Initialisation or configuration control processor initialisation G06F9/4405
• CPC Class Codes: G06F 15/7835 on more than one IC chip
• CPC Class Codes: G06F 15/786 using a single memory module
• CPC Class Codes: G06F 15/8015 One dimensional arrays, e.g. rings, linear arrays, buses
• CPC Class Codes: G06F 30/30 Circuit design
• CPC Class Codes: G06F 8/34 Graphical or visual programming
• CPC Class Codes: G06F 9/3016 Decoding the operand specifier, e.g. specifier format
• CPC Class Codes: G06F 9/30167 of immediate specifier, e.g. constants
• CPC Class Codes: G06F 9/325 for loops, e.g. loop detection or loop counter
• CPC Class Codes: G06F 9/355 Indexed addressing
• CPC Class Codes: G06F 9/38 Concurrent instruction execution, e.g. pipeline or look ahead
• CPC Class Codes: G06F 9/3877 using a slave processor, e.g. coprocessor peripheral processor G06F13/12; vector processor G06F15/8053

Abstract

Architectures and methods are provided for efficiently dividing a processing task into tasks for a programmable real time signal processor (SPROC) and tasks for a decision-making microprocessor. The SPROC is provided with a non-interrupt structure where data flow is through a multiported central memory. The SPROC is also programmed in an environment which requires nothing more than graphic entry of a block diagram of the user'"'"'s design. In automatically implementing the block diagram into silicon, the SPROC programming/development environment accounts for and provides software connection and interfaces with a host microprocessor. The programming environment preferably includes: a high-level computer screen entry system which permits choosing, entry, parameterization, and connection of a plurality of functional blocks; a functional block cell library which provides source code representing the functional blocks; and a signal processor scheduler/compiler which uses the functional block cell library and the information entered into the high-level entry system to compile a program and to output source program code for a program memory and source data code for the data memory of the (SPROC), as well as a symbol table which provides a memory map which maps SPROC addresses to variable names which the microprocessor will refer to in separately compiling its program.

Claims

1. Apparatus for use in linking the object code of a host processor with memory locations in a memory of a programmable signal processor to permit the host processor to partially control the programmable signal processor, where the object codes of the host processor and the signal processor are produced by separate compilation, said apparatus comprising:

a) means for symbolically describing a processing task for said signal processor including means for symbolically indicating input to said processing task by said host processor; and

b) means for producing by compilation signal processor object code representing said processing task for said signal processor, said means for producing by compilation being coupled to said means for symbolically describing and including means for producing a correspondence table in a format usable by a host processor code compiler, said correspondence table including a list of memory addresses in said programmable signal processor memory to be written to by said host processor in order to partially control said programmable signal processor.

2. Apparatus according to claim 1, wherein:

said means for symbolically describing includes a plurality of symbolic objects representing steps in said processing task and means for defining connections between symbolic objects, at least one of said symbolic objects indicating input by said host processor.

3. Apparatus according to claim 2, wherein:

said means for producing by compilation signal processor object code includes means for translating said symbolic objects and said connections between symbolic objects into object code for said signal processor, said object code being loaded into said signal processor memory, a portion of said code representing input by said host processor.

4. Apparatus according to claim 1, wherein:

said means for symbolically describing further includes means for indicating output from said processing task to said host processor; and

said correspondence table further includes a list of memory addresses in said programmable signal processor memory to be read by said host processor in order to partially control said programmable signal processor.

5. Apparatus according to claim 1, wherein:

said processing task includes at least one function having a parameter and said input by said host processor supplies a value for said parameter.

6. Apparatus for defining host processor access to tasks of a programmable signal processor, signal processor having a memory, wherein programs for said signal processor and said host processor are separately compiled, said apparatus comprising:

a) high level programming means for defining said tasks for said signal processor as a plurality of functional blocks, each said functional block comprising at least one aspect selected from the group of aspects consisting of a parameter, a function, an input, and an output, said high level programming means including means for identifying at least one of said functional block aspects of at least one of said functional blocks to be accessed by said host processor;

b) signal processor program compiler means coupled to said high level programming means for generating program code implementing said tasks, and for generating a list of memory locations of said code implementing said functional block aspects identified as accessible by said host processor.

7. Apparatus according to claim 6, wherein:

access by said host processor is selected from the group consisting of reading a parameter value, writing a parameter value, reading a function definition, writing a function definition, reading an output value, reading an input value, writing an output value and writing an input value.

8. Apparatus according to claim 7, wherein:

one of said functional block aspects is read by said host processor and another one of said functional block aspects is written by said host processor.