Video subsystem power management apparatus and method

• US 5,524,249 A
• Filed: 01/27/1994
• Issued: 06/04/1996
• Est. Priority Date: 01/27/1994
• Status: Expired due to Term

• Current Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Original Assignee: Compaq Computer Corporation (HP Inc.)
• Inventors: Suboh, Abdel H.
• Primary Examiner(s): Harvey, Jack B.
• Assistant Examiner(s): Travis, John
• Application Number:
  US08/191,311
• Time in Patent Office: 859 Days
• Field of Search: 395/750
• US Class Current: 713/322
• CPC Class Codes: G06F 1/3218 of display devices
• CPC Class Codes: G06F 1/3265 Power saving in display device
• CPC Class Codes: G09G 2330/022 in absence of operation, e.g. no data being entered during a predetermined time
• CPC Class Codes: G09G 5/36 characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

Power is conserved in a video subsystem by inactivating a pixel clock (PCLK) and reducing frequency of a memory clock (MCLK) responsive to an indication of user inactivity. The inactivation of PCLK reduces the power consumed in the RAMDAC, frame buffer, phase lock loop (PLL) clock circuit, and to a smaller extent, the video controller. Reducing the frequency of MCLK conserves power in the video controller and the PLL, In order to maintain the integrity of the data in the frame buffer, the refresh rate programmed by the video controller is increased to offset the reduction of the MCLK frequency. Significant power savings can be accomplished with minimal BIOS or video controller programming and minimal transfer of state information prior to power-down.

Claims

1. A method of reducing power consumption in a video subsystem of a computer, comprising the steps of:

inactivating a pixel clock which drives a RAMDAC, thereby reducing power consumed by the RAMDAC; and

decreasing the frequency of a memory clock for driving a video controller by a predetermined factor, thereby reducing the power consumed by the video controller.

2. The method of claim 1 and wherein said video controller refreshes a frame buffer at a programmable rate and further comprising the step of increasing the programmed refresh rate in the video controller by said predetermined factor, such that the reduction in the memory clock frequency to the video controller is offset by the increase in the programmed refresh rate, resulting in the frame buffer being refreshed at a normal refresh rate.

3. The method of claim 1 wherein said step of inactivating the pixel clock comprises the step of programming a phase lock loop clock circuit to disable generation of the pixel clock signal responsive to a data word from the video controller.

5. The method of claim 1 and further comprising the step of disabling a shift clock to a plurality of VRAMs forming a frame buffer.

6. The method of claim 1 wherein said step of decreasing the frequency of a memory clock to the video controller thereby reduces the frequency of memory cycles in a frame buffer, reducing the power consumed by the frame buffer.

4. The method of claim I wherein said step of decreasing the memory clock frequency comprises the step of programming a phase lock loop clock circuit to output a clock at a predetermined frequency responsive to a data word from the video controller.

7. A method of reducing power consumption in a video subsystem of a computer, comprising the steps of:

increasing the rate at which a video controller refreshes memory in a frame buffer by a predetermined factor; and

decreasing the frequency of a memory clock for driving the video controller by the predetermined factor, thereby reducing the power consumed by the video controller and reducing the frequency of memory cycles to a frame buffer, while maintaining a normal refresh rate.

8. The method of claim 7 and further comprising the step of inactivating a pixel clock which drives a RAMDAC, thereby reducing power consumed by the RAMDAC.

9. The method of claim 8 wherein said step of inactivating the pixel clock comprises the step of programming a phase lock loop clock circuit to disable generation of the pixel clock signal responsive to a data word from the video controller,

10. The method of claim 7 and further comprising the step of inactivating a shift clock for driving the output of said frame buffer responsive to said step of inactivating the pixel clock.

11. The method of claim 7 wherein said step of decreasing the memory clock frequency comprises the step of programming a phase lock loop clock circuit to output a clock at a predetermined frequency responsive to a data word from the video controller.

12. Circuitry for providing a video subsystem with power conservation capabilities, comprising:

clock circuitry for programmably generating a first clock and a second clock, such that said first clock can be disabled responsive to a first control signal and said second clock can be reduced in frequency responsive to a second control signal;

a frame buffer memory;

a RAMDAC driven by said first clock coupled to said frame buffer, the power consumed by said RAMDAC dependent upon the frequency of said first clock;

a video controller driven by said second clock and coupled to said frame buffer, said video controller controlling memory cycles in said frame buffer responsive to said second clock; and

circuitry for inactivating said first clock and reducing the frequency of said second clock responsive to an indication of inactivity to reduce power consumption in said clock circuitry, said frame buffer and said RAMDAC.

13. The circuitry of claim 12 wherein said video controller comprises circuitry for refreshing the frame buffer at selectable rates.

14. The circuitry of claim 13 and further comprising circuitry for increasing the refresh rate of the frame buffer prior to reducing the frequency of said second clock.

15. The circuitry of claim 12 wherein said video controller further comprises circuitry for communicating with said clock circuitry for setting said second clock to a desired frequency.

16. The circuitry of claim 15 wherein said video controller further comprises circuitry for communicating with said clock circuitry for inactivating said first clock.

17. The circuitry of claim 12 wherein said frame buffer memory comprises a plurality of VRAMs.

18. The circuitry of claim 12 wherein said frame buffer memory comprises a plurality of DRAMs.

19. A computer system for minimizing power consumption in a video subsystem comprising:

a CPU connected to a bus;

a plurality of peripherals connected to said CPU by the bus; and

a video subsystem connected to a video monitor and connected to said CPU by the bus, comprising;

a frame buffer comprising dynamic memory;

a clock circuit for generating a PCLK clock and a MCLK clock, and for disabling said PCLK clock and for decreasing a frequency of said MCLK clock in response to an inactivity signal;

a RAMDAC, connected to said frame buffer and to said clock circuit, driven by said PCLK clock; and

a video controller, driven by said MCLK clock, for programmably controlling a dynamic memory refresh rate of said frame buffer and for increasing the dynamic memory refresh rate to offset a decrease in the frequency of said MCLK clock in order to maintain the normal refresh rate of the dynamic memory.

20. The computer system of claim 19 wherein said video controller further comprises power management circuitry comprising a plurality of configuration registers for controlling the clock circuitry.

21. The system of claim 19 wherein said clock circuitry further comprises at least one PCLK register for controlling the frequency of the first clock and at least one MCLK register for controlling the frequency of the second clock.