Digital I/O bus controller circuit with auto-incrementing, auto-decrementing and non-incrementing/decrementing access data ports

• US 5,524,267 A
• Filed: 03/31/1994
• Issued: 06/04/1996
• Est. Priority Date: 03/31/1994
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Chin, Arthur L., Keener, Don S., Moore, Gregory J., Stine, Eric S., Payne, Stephanie P., Garcia, Serafin J. E. Jr.
• Primary Examiner(s): Robertson, David L.
• Application Number:
  US08/220,793
• Time in Patent Office: 796 Days
• Field of Search: 395/309, 395/310, 395/823, 395/824, 395/835, 395/837, 395/867, 395/868, 395/866, 365/189.03
• US Class Current: 710/3
• CPC Class Codes: G06F 13/22 using successive scanning, e.g. polling G06F13/24 takes precedence

Abstract

A digital bus circuit having an Address/Data port select decoder 170 in circuit communication with a Selector 194, a Data Port Buffer/Register 181, and an Address Port register 208. The Selector 194 is in circuit communication with an auto incrementor 216, an auto decrementor 218, and a polling function. The incrementor 216 serves to automatically increment an address present in the Address port register 208. The decrementor 218 serves to automatically decrement an address present in the Address port register 208. The polling function serves to reload the Address port register 208 with the same address. The present invention allows a number of enhanced programming methods which permit input and output operations to be implemented with fewer program code instructions. One of the programming methods disclosed by the present invention is an enhanced method of "polling" a device'"'"'s internal register by accessing the polling function.

Claims

1. A device for use in a computer system having a CPU coupled to a data bus and an address bus comprising:

(a) a first address decoder configured to be placed in circuit communication with the CPU via the address bus and further configured to decode the address bus into a first signal corresponding to a first address on the address bus and a second signal corresponding to a second address on the address bus;

(b) a plurality of registers each of which is configured to store a data value and which is accessible by the CPU via the data bus;

(c) a register pointer in circuit communication with said plurality of registers, configured to store a pointer value, and further configured to select any one of said plurality of registers responsive to the pointer value stored in said register pointer;

(d) pointer generation circuitry in circuit communication with said address decoder and said register pointer and configured to modify the register pointer responsive to an access of said first address of the address bus and further configured to preserve the state of said register pointer responsive to an access of said second address of the address bus.

2. The device of claim 1 wherein said pointer generation circuity is configured to increment the register pointer responsive to access of said first signal.

3. The device of claim 1 wherein said pointer generation circuity is configured to decrement the register pointer responsive to access of said first signal.

4. The device of claim 1 wherein said register pointer comprises:

(a) a writable register in circuit communication with the data bus and

(b) a second address decoder in circuit communication with said writable register and said plurality of registers.

5. The device of claim 1 wherein said pointer generation circuitry comprises:

a selector in circuit communication with said first address decoder, a pass-through, and counter all of which are in circuit communication with said register pointer.

6. The device of claim 5 wherein said counter is in the form of an incrementor.

7. The device of claim 5 wherein said counter is in the form of a decrementor.

8. The device of claim 1 wherein said pointer generation circuitry comprises:

a selector in circuit communication with said address decoder, a pass-through, an incrementor, and a decrementor all of which are in circuit communication with said register pointer.

9. A method of using a CPU to access data stored within a plurality of registers, wherein the CPU is coupled to an address bus and a data bus, comprising the steps of:

(a) providing a register pointer in circuit communication with said plurality of registers, configured to store a pointer value, and further configured to select any one of said plurality of registers responsive to the pointer value stored in said register pointer

(b) providing an address decoder in circuit communication with said register pointer and configured to decode the address bus into a first signal corresponding to a first address on the address bus and a second signal corresponding to a second address on the address bus;

(c) accessing via the data bus the contents of the register of said plurality of registers pointed to by said register pointer responsive to accesses of said first and second addresses of the address bus;

(d) modifying said register pointer responsive to an access of said first address of the address bus; and

(e) preserving the state of said register pointer responsive to an access of said second address of the address bus.

10. The device of claim 9 wherein modifying said register pointer responsive to an access of said first address includes incrementing.

11. The device of claim 9 wherein modifying said register pointer responsive to an access of said first address includes decrementing.

12. A method of using a CPU to access data stored within a plurality of registers, wherein the CPU is coupled to an address bus and a data bus, comprising the steps of:

(a) providing a register pointer in circuit communication with said plurality of registers, configured to store a pointer value, and further configured to select any one of said plurality of registers responsive to the pointer value stored in said register pointer;

(b) providing an address decoder in circuit communication with said register pointer and configured to decode the address bus into a first signal corresponding to a first address on the address bus, a second signal corresponding to a second address on the address bus, and a third signal corresponding to a third address on the address bus;

(c) accessing via the data bus the contents of the register of said plurality of registers pointed to by said register pointer responsive to accesses of said first, second, and third addresses of the address bus;

(d) incrementing said register pointer responsive to an access of said first address of the address bus;

(e) decrementing said register pointer responsive to an access of said second address of the address bus; and

(f) preserving the state of said register pointer responsive to an access of said third address of the address bus.

13. A method of "polling" a devices internal register comprising:

(a) loading an address port with a device'"'"'s internal register address that is to be "polled" via a first program instruction,

(b) reading said device'"'"'s internal register by reading from a polling data port via a second program instruction,

(c) loading said address port with said device'"'"'s internal register address automatically without having to use a program instruction,

(d) testing data read from said device'"'"'s internal register address via a third program instruction, and

(e) repeating steps (b), (c), and (d) without repeating step (a) until said testing in step (d) is satisfied.