Method for reducing dopant diffusion

• US 5,525,529 A
• Filed: 11/16/1994
• Issued: 06/11/1996
• Est. Priority Date: 11/16/1994
• Status: Expired due to Term

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Guldi, Richard L.
• Primary Examiner(s): Chaudhari, Chandra
• Application Number:
  US08/340,770
• Time in Patent Office: 573 Days
• Field of Search: 437/28, 437/95, 437/931, 437/976, 437/34, 148/DIG. 7
• US Class Current: 438/565
• CPC Class Codes: H01L 21/2652 Through-implantation
• CPC Class Codes: H01L 21/823814 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 29/6659 with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
• CPC Class Codes: Y10S 148/007 Autodoping
• CPC Class Codes: Y10S 438/902 Capping layer
• CPC Class Codes: Y10S 438/976 Temporary protective layer

Abstract

A process is disclosed for inhibiting undesired diffusion of implanted dopants during and after dopant activation, as can occur during source/drain anneal. Undesired dopant diffusion is minimized by a dopant blocking layer, which is applied to the semiconductor body prior to dopant activation, and preferably prior to dopant implantation. The composition of the blocking layer is selected in accordance with the diffusion mechanism of the dopant to be implanted so that the concentration of lattice vacancies or interstitials (depending upon the dopant diffusion mechanism) is reduced, thereby inhibiting undesired migration of the implanted species.

Claims

1. A process for inhibiting dopant diffusion in a semiconductor material, comprising the steps of:

a. providing a semiconductor body having an upper surface and at least one unimplanted region devoid of dopant;

b. selecting a dopant for introduction into said semiconductor body to form at least one active region in said unimplanted region;

c. providing a dopant blocking layer in overlying relation with said at least one active region and introducing by way of a diffusion mechanism utilizing one of lattice vacancies or interstitial sites into said active region in accordance with the diffusion mechanism of said selected dopant;

d. introducing said selected dopant through said blocking layer and into said semiconductor body; and

e. activating said introduced dopant by heating said semiconductor body.

2. The process according to claim 1, wherein said interstitial sites or lattice vacancies are introduced by adjusting the composition of said blocking layer.

3. The process according to claim 1, further comprising the step of applying a screen insulating layer prior to provision of said blocking layer.

4. The process according to claim 3, further comprising the step of removing said screen insulating layer prior to dopant activation.

5. The process according to claim 1, wherein said step of activating said implanted dopant comprises heating said semiconductor body to a temperature of at least about 800°

C.

6. The process according to claim 1, wherein said dopants are introduced into said semiconductor body to create discrete source/drain regions.

7. The process according to claim 3, wherein said screen insulating layer comprises an oxide, nitride or oxynitride having a thickness of about 20-40 nm.

8. The process according to claim 1, wherein said blocking layer comprises a native oxide having a thickness of about 1-3 nm.

9. The process according to claim 1, wherein said semiconductor body is heated in an ammonia atmosphere.

10. The process according to claim 1, wherein said blocking layer comprises a silicon deficient oxide having the composition SiO_x, in which x>

2.

11. The process according to claim 1, wherein said blocking layer comprises a silicon deficient oxynitride having the composition SiO_u N_v that underlies a silicon nitride film, in which "u" and "v" represent fractional components selected to render a silicon deficient film.

12. The process according to claim 1, wherein said blocking layer comprises a screen oxide or a screen oxynitride having a thickness of about 5-50 nm and the semiconductor body is heated in an ammonia atmosphere.

13. The process according to claim 1, wherein said blocking layer comprises an oxide film that underlies a silicon nitride film having the composition Si₃ N_y, in which y>

4.

14. The process according to claim 13, wherein the silicon nitride is applied by one of plasma deposition or low pressure chemical vapor deposition utilizing an NH₃ :

SiH₂ Cl₂ ratio of at least about 10;

1.

15. The process according to claim 13, wherein said oxide film is applied by one of thermal oxidation or plasma-assisted deposition.

16. The process according to claim 1, wherein said blocking layer comprises a silicon nitride film having an SiO₂ overlay film which, in turn, underlies an Si₃ N₄ film.

17. The process according to claim 16, wherein said lowermost silicon nitride film is applied by one of low pressure chemical vapor deposition or plasma enhanced deposition.

18. A process for inhibiting dopant diffusion in a semiconductor material comprising the steps of:

a. providing a semiconductor body having an upper surface and at least one unimplanted region devoid of dopant;

b. selecting a dopant for introduction into said semiconductor body to form at least one active region in said unimplanted region;

c. introducing said dopant into said semiconductor body in a direction substantially transverse to said upper surface;

d. providing a blocking layer in overlying relation with said at least one active region and introducing by way of a diffusion mechanism utilizing one of lattice vacancies or interstitial sites into said active regions in accordance with the diffusion mechanism of said selected dopant; and

e. activating said implanted dopant by heating said semiconductor body.

19. The process according to claim 18, further comprising the step of applying a screen insulating layer to said semiconductor body upper surface prior to introduction of said dopant.

20. The process according to claim 19, wherein said step of activating said implanted dopant comprises heating said semiconductor body to a temperature of at least about 800°

C.