×

Integrated circuit package

  • US 5,525,834 A
  • Filed: 10/17/1994
  • Issued: 06/11/1996
  • Est. Priority Date: 10/17/1994
  • Status: Expired due to Term
First Claim
Patent Images

1. An integrated circuit package for housing an integrated circuit chip and for providing electrical connectivity of data signals and voltage signals between the integrated circuit chip and an electronic component, the package comprising:

  • a carrier substrate having a first surface including a die attach region and a signal layer region;

    an integrated circuit chip affixed to the die attach region, the integrated circuit chip including a plurality of bonding pads;

    at least three conductive layers on the signal layer region of the substrate for conducting electrical signals, the conductive layers comprising a single signal layer, at least a first voltage layer for providing a first reference voltage signal to the integrated circuit chip and a second voltage layer for providing a second reference voltage signal to the integrated circuit chip, the first voltage layer comprising a reference ground layer adjacent to the substrate for providing a ground signal to the integrated circuit chip and the second voltage layer comprising a reference voltage layer closely coupled to the reference ground layer thereby providing a predetermined significant level of decoupling capacitance therebetween;

    a plurality of bond wires having a predetermined length, each bond wire electrically connecting a single bonding pad of the integrated circuit chip to a single bonding pad of the signal layer each bond wire being disposed parallel one to each other to route all of the data signals on the single signal layer to minimize the length of the bond wires;

    at least first and second dielectric layers, each dielectric layer having a predetermined dielectric constant, the at least first dielectric layer being disposed between the first and second voltage layers, and the at least second dielectric layer being disposed between the second voltage layer and the signal layer, the dielectric constant of the at least second dielectric layer being less than the dielectric constant of the first layer; and

    a plurality of electrical connections for interconnecting the chip bonding pads with the electronic component by way of at least one of the conductive layers for conducting electrical signals therebetween.

View all claims
  • 2 Assignments
Timeline View
Assignment View
    ×
    ×