Single event upset immune register with fast write access

• US 5,525,923 A
• Filed: 02/21/1995
• Issued: 06/11/1996
• Est. Priority Date: 02/21/1995
• Status: Expired due to Term

• Current Assignee: BAE Systems Information and Electronic Systems Integration Incorporated (BAE Systems Plc)
• Original Assignee: Loral Federal Systems Company
• Inventors: Bialas, Jr., John S., Hoffman, Joseph A.
• Primary Examiner(s): Callahan, Timothy P.
• Assistant Examiner(s): ADOLPHE, EUNJA
• Application Number:
  US08/391,798
• Time in Patent Office: 476 Days
• Field of Search: 327/210, 327/199, 327/200, 327/201, 327/202, 327/203, 327/208, 327/211, 327/212, 327/214, 327/218, 365/154, 365/156
• US Class Current: 327/210
• CPC Class Codes: G11C 11/4125 Cells incorporating circuit means for protecting against loss of information
• CPC Class Codes: H03K 3/0375 provided with means for increasing reliability; for protection; for ensuring a predetermined initial state when the supply voltage has been applied; for storing the actual state when the supply voltage fails digital storage cells each combining volatile and non-volatile storage properties G11C14/00

Abstract

A single event upset hardened bi-stable CMOS circuit has a pair of cross coupled invertors with an isolation resistor in the path coupling the drains of the transistors in each invertor. Each invertor includes a PFET and a NFET pair coupled source to drain. An isolation resistor couples together the drains of each PFET-NFET pair and two low impedance conductive paths provide a direct coupling between the drains of each transistor of one invertor to common gate node of the other invertor.

Claims

1. A single event upset hardened bi-stable circuit comprising in combination:

a first complementary pair of CMOS semiconductor transistors including a first PMOS transistor and a first NMOS transistor with a first isolation resistor coupling a drain node of said first PMOS transistor to a drain node of said first NMOS transistor;

a second complementary pair of CMOS semiconductor transistors including a second PMOS transistor and a second NMOS transistor with a second isolation resistor coupling a drain node of said second PMOS transistor to a drain node of said second NMOS transistor;

first low impedance means coupling said drain node of said first PMOS transistor to a gate of said second PMOS transistor;

second low impedance means coupling said drain node of said first NMOS transistor to a gate of said second NMOS transistor

third low impedance means coupling said drain node of said second PMOS transistor to a gate of said first PMOS transistor;

fourth low impedance means coupling said drain node of said second NMOS transistor to a gate of said first NMOS transistor;

write input means coupled to a gate electrode of said first PMOS transistor and a gate electrode of said first NMOS transistor.

2. A single event upset hardened bi-stable circuit as in claim 1, wherein said first isolation resistor and said second isolation resistor limit a change in potential at one node of said first complementary pair of CMOS semiconductor transistors and said second pair of complementary CMOS semiconductor transistors, respectively due to a particle strike caused change of potential in a corresponding node of said first complementary pair of CMOS semiconductor transistors and said second pair of complementary CMOS semiconductor transistors, respectively.

3. A single event upset hardened bi-stable circuit as in claim 1 wherein said write input means includes a first pair of CMOS transmission gates and a second pair of CMOS transmission gates to write to said first complementary pair of CMOS semiconductor transistors and said second pair of CMOS semiconductor transistors, bypassing said first isolation resistor and said second isolation resistor during write operations.

4. A single event upset hardened bi-stable circuit as in claim 2 wherein said write input means includes a first pair of CMOS transmission gates and a second pair of CMOS transmission gates to write to said first complementary pair of CMOS semiconductor transistors and said second pair of CMOS semiconductor transistors, bypassing said first isolation resistor and said second isolation resistor during write operations.