Sure chip

• US 5,525,985 A
• Filed: 12/28/1990
• Issued: 06/11/1996
• Est. Priority Date: 12/28/1990
• Status: Expired due to Term

• Current Assignee: Eaton Corp. (Wisconsin) (Eaton Corporation PLC.)
• Original Assignee: Eaton Corp. (Wisconsin) (Eaton Corporation PLC.)
• Inventors: Elms, Robert T., Schlotterer, John C.
• Primary Examiner(s): Young, Brian K.
• Application Number:
  US07/636,643
• Time in Patent Office: 1,992 Days
• Field of Search: 341/136, 341/139, 341/141, 341/155, 341/133, 341/135
• US Class Current: 341/136
• CPC Class Codes: G06J 1/00 Hybrid computing arrangements digitally-programmed analogue computers G06G7/06
• CPC Class Codes: H02H 6/005 using digital thermal images
• CPC Class Codes: H03M 1/186 in feedforward mode, i.e. by determining the range to be selected directly from the input signal

Abstract

A hybrid monolithic IC that is standardized for controlling various types of electrical equipment, such as circuit breakers, motor controllers and the like. The IC is a hybrid monolithic IC, fabricated in CMOS technology. The shortcomings of utilizing CMOS technology for linear or analog circuitry is overcome by the implementation of the IC to provide a hybrid monolithic IC that is relatively less expensive than using multiple IC'"'"'s or a single IC fabricated from biCMOS technology. Also, by utilizing a single IC, such control and monitoring circuitry can be located in existing electrical equipment. The IC includes an on-board microprocessor, an A/D subsystem and various input/output devices which make it adaptable for use in various types of electrical equipment. In order to improve the resolution of the A/D subsystem, circuitry is provided, which includes current and voltage ranging amplifiers for ranging analog input voltage and current signals and compensating internal offsets, in such amplifiers, inherent in CMOS linear circuits which can affect the accuracy of the least significant bit. The ranging circuitry is controlled either automatically or manually to provide additional resolution of the A/D subsystem.

Claims

1. A CMOS monolithic circuit comprising:

an analog subsystem including analog receiving means for receiving analog signals;

a digital subsystem including digital receiving means for receiving digital signals;

producing means interconnected with said analog receiving means and said digital receiving means for producing an output signal responsive to said analog subsystem or said digital subsystem; and

means for resetting said digital subsystem responsive to said analog subsystem and said digital subsystem.

2. A CMOS monolithic circuit as recited in claim 1, further including an analog power supply means for providing a first predetermined voltage to said analog subsystem and digital power supply means for providing a second predetermined voltage to said digital subsystem.

3. A CMOS monolithic circuit as recited in claim 2, wherein said resetting means includes means for monitoring said first predetermined voltage and resetting said digital subsystem when said first predetermined voltage falls below a predetermined value.

4. A CMOS monolithic circuit as recited in claim 2, wherein said resetting means includes means for monitoring said second predetermined voltage and resetting said digital subsystem when said second predetermined voltage falls below a predetermined value.

5. A CMOS monolithic circuit as recited in claim 2, wherein said resetting means includes means for monitoring said first and second predetermined voltages and resetting said digital subsystem whenever said first or second predetermined voltages fall below a predetermined value.

6. A CMOS monolithic circuit comprising:

an analog subsystem including analog receiving means for receiving differential input signals and producing an output signal as a predetermined function of said input signals and bias currents internally generated by said receiving analog means which control an input offset voltage to said analog receiving means;

a digital subsystem including digital receiving means for receiving digital signals;

producing means interconnected with said analog receiving means and said digital receiving means for producing an output signal responsive to said analog or digital subsystems; and

means for controlling said bias currents.

7. A CMOS monolithic circuit as recited in claim 6, wherein said controlling means is responsive to said digital subsystem.

8. A CMOS monolithic circuit as recited in claim 7, wherein said controlling means includes means for isolating said output signal and said differential input signals.

9. A CMOS monolithic circuit as recited in claim 7, wherein said controlling means includes means grounding said inputs.

10. A CMOS monolithic circuit as recited in claim 7, wherein controlling means includes means for varying said bias currents in discrete steps until said output signal is at a predetermined value.

11. A CMOS monolithic circuit as recited in claim 6, wherein said controlling means includes means for maintaining said bias currents at a predetermined value.

12. A CMOS monolithic circuit as recited in claim 11, wherein said digital subsystem includes a microprocessor.

13. A CMOS monolithic circuit as recited in claim 12, wherein said maintaining means is addressable by said microprocessor.

14. A CMOS monolithic integrated circuit comprising:

securing means for securing digital input signals;

receiving means for receiving analog signals;

producing means interconnected with said securing means and said receiving means for producing digital output signals as a predetermined function of said analog signals or said digital signals; and

disabling means for disabling said producing means as a predetermined function of said receiving means.