Method and apparatus for converting field-programmable gate array implementations into mask-programmable logic cell implementations

• US 5,526,278 A
• Filed: 06/20/1995
• Issued: 06/11/1996
• Est. Priority Date: 12/30/1993
• Status: Expired due to Term

• Current Assignee: Lattice Semiconductor Corporation
• Original Assignee: AT&T Corporation (AT&T, Inc.)
• Inventors: Powell, Gary P.
• Primary Examiner(s): Trans, Vincent N.
• Application Number:
  US08/492,604
• Time in Patent Office: 357 Days
• Field of Search: 364/488, 364/489, 364/490, 326/37, 326/38, 340/828.83
• US Class Current: 716/55
• CPC Class Codes: G06F 30/30 Circuit design
• CPC Class Codes: G06F 30/39 Circuit design at the physical level physical level design for reconfigurable circuits G06F30/347
• CPC Class Codes: G06F 30/396 Clock trees

Abstract

A method and system, in which the relative physical placement of configurable logic blocks, signal routing networks, and clock distribution trees of the FPGA implementation is preserved on the mask programmable logic cell (MPLC) substrate after the conversion process is completed. By constraining the physical placement of corresponding structures on the MPLC substrate at the network level of the MPLC implementation, the relative signal and clock delays presented during the FPGA implementation are substantially maintained in the MPLC implementation, thereby assuring functional equivalence between the FPGA and MPLC implementations.

Claims

1. A method of converting a field-programmable gate array (FPGA) implementation of a digital logic design, into a mask-programmable logic cell (MPLC) implementation of said digital logic design, the method comprising the steps of:

(a) selecting a FPGA device and a FPGA library for use in achieving said FPGA implementation, said FPGA device including a package containing a substrate carrying

a plurality of a programmable input and output interface blocks (IOBs) each having input and output ports operably associated with a plurality of pins on said package and programmable logic circuitry contained therein,

a plurality of programmable configurable logic blocks(CLBs) each having input and output ports and programmable logic circuitry contained therein,

a plurality of programmable interconnect switches for selectively interconnecting the input and output ports of said CLBs and the input and output ports of said IOBs so to form a first signal network for routing signals within said FPGA device with first set of signal delays,

(b) generating a FPGA netlist for said FPGA implementation, said hierarchical FPGA netlist containing a CLB description for each said CLB utilized in said FPGA implementation, an IOB description for each said IOB utilized in said FPGA implementation, and port connectivity specifications specifying the interconnections to be established between the input and output ports of said utilized CLBs and said utilized IOBs, effectuated by said plurality of programmable interconnect switches, in order to form said first signal network within said FPGA device;

(c) selecting a MPLC device and a MPLC library for use in achieving said MPLC implementation, said MPLC device including a package containing a substrate having at least one interconnect level and an array of a logic cells which can be selectively configured at said at least one interconnect level to form a plurality of Soft-CLBs and a plurality of Soft-IOBs on said MPLC substrate, wherein each said Soft-CLB and each said Soft-IOB has input and output ports interconnectable at said at least one interconnect level by applying a metalization layer of computable geometry to said MPGA substrate, in order to form a second signal network for routing signals within said MPLC device with a second set of signal delays said second signal network physically corresponding to said first signal network;

(d) generating a MPLC netlist for said MPLC implementation, said MPLC netlist containing hierarchical information regarding said MPLC implementation including

a Soft-CLB description for each said Soft-CLB to be formed on said MPLC substrate,

a Soft-CLB connectivity description specifying the connectivity of the input and output ports of said Soft-CLBs specified in said MPLC netlist,

a Soft-IOB description for each said Soft-IOB to be formed on said MPLC substrate, and

a Soft-IOB connectivity description specifying the connectivity of the input and output ports of said Soft-IOBs specified in said MPLC netlist;

(e) using said modified MPLC netlist and said MPLC library to generate a geometrical database containing

geometrical information specifying the physical placement of each said Soft-CLB and each said Soft-IOB on said MPLC substrate, and

geometrical information specifying the signal paths on said MPLC substrate interconnecting the input and output ports of said CLBs and IOBs in accordance with said Soft-CLB connectivity description and said Soft-IOB connectivity description, such that the relative signal delays presented during said FPGA implementation are substantially maintained in said MPLC implementation, thereby assuring functional equivalence between said FPGA and MPLC implementations.

2. The method of claim 1, wherein step (a), said selected FPGA device further comprises

a clock signal producing means for producing clock signals for use by said CLBs and IOBs,

a clock signal distribution structure having a first plurality of conductive elements for routing within said clock signals to said CLBs and IOBs,

and wherein said method further comprises after step (d),

producing a modified MPLC netlist by adding to said MPLC netlist, a description of said clock signal producing means on said MPLC substrate and a description of said clock signal distribution structure on said MPLC substrate;

and wherein said geometrical database further comprises geometrical information specifying the physical placement of said clock signal producing means and said reset signal producing means on said MPLC substrate, and also geometrical information specifying the physical routing of said clock signal distribution structure on said MPLC substrate.

3. The method of claim 1, which further comprises during step (d),

adding to said modified MPLC netlist, a Soft-CLB load for each said CLB in said FPGA device not utilized in realizing said FPGA implementation.

4. The method of claim 3, which further comprises

(f) using said geometrical database to produce a set of photolithic processing masks for use in forming said metalization layer on said MPGA substrate.

5. The method of claim 4, which further comprises

(g) using said produced set of photolithic processing masks to form said metalization layer on said MPGA substrate.

6. The method of claim 1, wherein said MPLC implementation is a mask-programmable gate array(MPGA) implementation, wherein and said MPLC device is a MPGA device, and said MPLC library is a MPGA library.

7. The method of claim 1, wherein said MPLC implementation is a mask-programmable standard cell(MPSC) implementation, wherein and said MPLC device is a MPSC device, and said MPLC library is a MPSC library.

8. The method of claim 2, where during the production of said geometrical database, said each said Soft-CLB is placed at a physical location on said MPLC substrate which is relatively the same as the physical location of the corresponding CLB on said FPGA substrate, wherein each said Soft-IOB is placed at a physical location on said MPLC substrate which is relatively the same as the physical location of the corresponding IOB on said FPGA substrate, wherein each said clock signal producing means on said MPLC substrate is placed at a physical location on said MPLC substrate which is relatively the same as the physical location of the corresponding clock signal producing means on said FPGA substrate, and wherein the physical routing of said clock signal distribution structure on said MPLC substrate is routed along a signal route on said MPLC substrate which is relatively the same as the signal route of the corresponding clock distribution structure on said FPGA substrate.

9. A method of converting a field-programmable gate array (FPGA) implementation of a digital logic design, into a mask-programmable logic cell (MPLC) implementation of said digital logic design, the method comprising the steps of:

(a) selecting a FPGA device and a FPGA library for use in achieving said FPGA implementation, said FPGA device including a package containing a substrate carrying

a plurality of a programmable input and output interface blocks (IOBs) each having input and output ports operably associated with a plurality of pins on said package and programmable logic circuitry contained therein,

a plurality of programmable configurable logic blocks (CLBs) each having input and output ports and programmable logic circuitry contained therein,

a plurality of programmable interconnect switches for selectively interconnecting the input and output ports of said CLBs and the input and output ports of said IOBs so to form a first signal network for routing signals within said FPGA device with a first set of signal delays,

a clock signal producing means for producing clock signals for use by said CLBs and IOBs, and

a clock signal distribution structure having a first plurality of conductive elements for routing within said clock signals to said CLBs and IOBs,

(b) generating a FPGA netlist for said FPGA implementation, said FPGA netlist containing hierarchial information, including a CLB description for each said CLB utilized in said FPGA implementation, an IOB description for each said IOB utilized in said FPGA implementation, and port connectivity specifications specifying the interconnections to be established between the input and output ports of said utilized CLBs and said utilized IOBs, effectuated by said plurality of programmable interconnect switches, in order to form said second signal network within said FPGA device;

(c) selecting a MPLC device and a MPLC library for use in achieving said MPLC implementation, said MPLC device including a package containing a substrate having at least an interconnect level and carrying an array of a logic cells which can be selectively configured at said at least interconnect level to form a plurality of Soft-CLBs and a plurality of Soft-IOBs on said MPLC substrate, wherein each said Soft-CLB and each said Soft-IOB has input and output ports that can be interconnected at said interconnect level by applying a metalization layer of computed geometry to said MPGA substrate, in order to form a second signal network for routing signals within said MPLC device with a second set of signal delays, said second signal network physically corresponding to said first signal network;

(d) generating a MPLC netlist for said MPLC implementation, said MPLC netlist including

a Soft-CLB description for each said Soft-CLB to be formed on said MPLC substrate,

a Soft-CLB connectivity description specifying the connectivity of the input and output ports of said Soft-CLBs specified in said MPLC netlist,

a Soft-IOB description for each said Soft-IOB to be formed on said MPLC substrate, and

a Soft-IOB connectivity description specifying the connectivity of the input and output ports of said Soft-IOBs specified in said MPLC netlist;

(e) producing a modified MPLC netlist by adding to said MPLC netlist,

(1) a Soft-CLB load for each said CLB in said FPGA device not utilized in realizing said FPGA implementation,

(2) a description of said clock signal producing means located on said MPLC substrate, and

(3) a description of said clock signal distribution structure located on said MPLC substrate,

(f) using said modified MPLC netlist and said MPLC library to generate a geometrical database containing

geometrical information regarding the physical placement of each said Soft-CLB, the physical placement of each said Soft-IOB, and the physical placement of said clock signal producing means on said MPLC substrate, and

geometrical information specifying the physical routing of said clock signal distribution structure, and the signal paths on said MPLC substrate interconnecting the input and output ports of said CLBs and IOBs in accordance with said Soft-CLB connectivity description and said Soft-IOB connectivity description, wherein the physical placement of said Soft-CLBs, said Soft IOBS, and said clock signal producing means on said MPLC substrate is the same as the relative physical placement of corresponding Soft-CLBs, corresponding Soft IOBS, and corresponding clock signal producing means on said FPGA substrate, such that the relative signal and clock delays presented during said FPGA implementation are substantially maintained in said MPLC implementation, thereby assuring functional equivalence between said FPGA and MPLC implementations.

10. The method of claim 9, which further comprises

(g) using said geometrical database to produce a set of photolithic processing masks for use in forming said metalization layer on said MPGA substrate.

11. The method of claim 10, which further comprises

(h) using said produced set of photolithic processing masks to form said metalization layer on said MPGA substrate.

12. The method of claim 9, wherein said MPLC implementation is a mask-programmable gate array (MPGA) implementation, wherein and said MPLC device is a MPGA device, and said MPLC library is a MPGA library.

13. The method of claim 9, wherein said MPLC implementation is a mask-programmable standard cell (MPSC) implementation, wherein and said MPLC device is a MPSC device, and said MPLC library is a MPSC library.

14. A computer-based system for converting a field-programmable gate array (FPGA) implementation of a digital logic design, into a mask-programmable logic cell (MPLC) implementation of said digital logic design, said computer-based system comprising:

information storage means for storing information, including information representative of a FPGA device and a FPGA library for use in achieving said FPGA implementation, said FPGA device including a package containing a substrate carrying

a plurality of a programmable input and output interface blocks (IOBs) each having input and output ports operably associated with a plurality of pins on said package and programmable logic circuitry contained therein,

a plurality of programmable configurable logic blocks (CLBs) each having input and output ports and programmable logic circuitry contained therein, and

a plurality of programmable interconnect switches for selectively interconnecting the input and output ports of said CLBs and the input and output ports of said IOBs so to form on said FPGA substrate a first signal network for routing signals within said FPGA device with determinable amounts of signal delay,

said information storage means further storing information representative of a selected MPLC device and a MPLC library used in realizing said MPLC implementation, said MPLC device including a package containing a MPLC substrate having at least one interconnect level and carrying an array of a logic cells selectively configurable at said at least one interconnect level to form a plurality of Soft-CLBs and a plurality of Soft-IOBs on said MPLC substrate, wherein each said Soft-CLB and each said Soft-IOB has input and output ports interconnectable at said at least one interconnect level by applying a metalization layer of computable geometry to said MPGA substrate, in order to form a second signal network for routing signals within said MPLC device with a determinable amount of signal delay, said first signal network physically corresponding to said second signal network;

programmed information processing means, operably associated with said information storage means, for generating a first data structure representative of a FPGA netlist for said FPGA implementation using said FPGA device, said FPGA netlist containing hierarchical information including a CLB description for each said CLB utilized in said FPGA implementation, an IOB description for each said IOB utilized in said FPGA implementation, and port connectivity specifications specifying the interconnections to be established between the input and output ports of said utilized CLBs and said utilized IOBs, effectuated by said plurality of programmable interconnect switches, in order to form said first signal network within said FPGA device,

said programmed information processing means further generating a second information structure representative of a MPLC netlist for said MPLC implementation using said MPLC device, said MPLC netlist containing hierarchical information including

a Soft-CLB description for each said Soft-CLB to be formed on said MPLC substrate,

a Soft-CLB connectivity description specifying the connectivity of the input and output ports of said Soft-CLBs specified in said MPLC netlist,

a Soft-IOB description for each said Soft-IOB to be formed on said MPLC substrate, and

a Soft-IOB connectivity description specifying the connectivity of the input and output ports of said Soft-IOBs specified in said MPLC netlist, and

said programmed information processing means further generating a geometrical database using said modified MPLC netlist and said MPLC library, said geometrical database containing

geometrical information specifying the physical placement of each said Soft-CLB, and each said Soft-IOB, said clock signal producing means, and

geometrical information specifying the physical routing of the signal paths on said MPLC substrate interconnecting the input and output ports of said CLBs and IOBs in accordance with said Soft-CLB connectivity description and said Soft-IOB connectivity description, such that the relative signal delays presented in said first signal network of said FPGA implementation are substantially maintained in said second signal network of said MPLC implementation, thereby assuring functional equivalence between said FPGA and MPLC implementations.

15. The computer-based system of claim 14, wherein said FPGA device further comprises

a clock signal producing means for producing clock signals for use by said CLBs and IOBs;

and

a clock signal distribution structure having a first plurality of conductive elements for routing within said clock signals to said CLBs and IOBs;

a reset signal producing means for producing a reset signal for use by said CLBs and said IOBs; and

wherein said computer-based system further comprises means for adding information to said second information structure so as to produce a modified MPLC netlist which further includes a description of said clock signal producing means on said MPLC substrate, and a description of said clock signal distribution structure on said MPLC substrate;

said programmed information processing means using said modified MPLC netlist and said MPLC library to generate additional geometrical information and to add said additional geometrical information to said geometrical database, said additional geometrical information further specifying the physical placement of said clock signal producing means on said MPLC substrate and also specifying the physical routing of said clock signal distribution structure on said MPLC substrate.

16. The computer-based system of claim 15, wherein said programmed information processing means further including means for adding to said modified MPLC netlist, a Soft-CLB load for each said CLB in said FPGA device not utilized in realizing said FPGA implementation.

17. The computer-based system of claim 15, which further comprises means for producing a set of photolithic processing masks, using said geometrical database.

18. The computer-based system of claim 17, which further comprises means for forming said metallization layer on said MPGA substrate, using said produced set of photolithic processing masks.

19. The computer-based system of claim 15, wherein said MPLC implementation is a mask-programmable gate array (MPGA) implementation, wherein and said MPLC device is a MPGA device, and said MPLC library is an MPGA library.

20. The computer-based system of claim 15, wherein said MPLC implementation is a mask-programmable standard cell (MPSC) implementation, wherein and said MPLC device is a MPSC device, and said MPLC library is an MPSC library.