Burst EDO memory device

• US 5,526,320 A
• Filed: 12/23/1994
• Issued: 06/11/1996
• Est. Priority Date: 12/23/1994
• Status: Expired due to Term

• Current Assignee: Round Rock Research LLC
• Original Assignee: Micron Technology, Inc.
• Inventors: Manning, Troy A., Williams, Brett L., Zagar, Paul S.
• Primary Examiner(s): Nelms, David C.
• Assistant Examiner(s): NGUYEN, TAN
• Application Number:
  US08/370,761
• Time in Patent Office: 536 Days
• Field of Search: 365/230.01, 365/230.06, 365/230.08, 365/238.5, 365/233.5, 365/235, 365/189.05, 365/236
• US Class Current: 365/233.5
• CPC Class Codes: G06F 12/0638 Combination of memories, e.g. ROM and RAM such as to permit replacement or supplementing of words in one module by words in another module address formation of the next microinstruction G06F9/26; masking faults in memories by using spares or by reconfiguring G11C29/70
• CPC Class Codes: G06F 2212/2022 Flash memory
• CPC Class Codes: G11C 11/407 for memory cells of the field-effect type
• CPC Class Codes: G11C 7/1018 Serial bit line access mode, e.g. using bit line address shift registers, bit line address counters, bit line burst counters
• CPC Class Codes: G11C 7/1021 Page serial bit line access mode, i.e. using an enabled row address stroke pulse with its associated word line address and a sequence of enabled column address stroke pulses each with its associated bit line address
• CPC Class Codes: G11C 7/1024 Extended data output [EDO] mode, i.e. keeping output buffer enabled during an extended period of time
• CPC Class Codes: G11C 7/1039 using pipelining techniques, i.e. using latches between functional memory parts, e.g. row/column decoders, I/O buffers, sense amplifiers
• CPC Class Codes: G11C 7/1045 Read-write mode select circuits
• CPC Class Codes: G11C 7/1078 Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
• CPC Class Codes: G11C 7/109 Control signal input circuits
• CPC Class Codes: G11C 7/1096 Write circuits, e.g. I/O line write drivers

Abstract

An integrated circuit memory device is designed for high speed data access and for compatibility with existing memory systems. An address strobe signal is used to latch a first address. During a burst access cycle the address is incremented internal to the device with additional address strobe transitions. A new memory address is only required at the beginning of each burst access. Read/Write commands are issued once per burst access eliminating the need to toggle the Read/Write control line at the device cycle frequency. Transitions of the Read/Write control line during a burst access will terminate the burst access, reset the burst length counter and initialize the device for another burst access. The device is compatible with existing Extended Data Out DRAM device pinouts, Fast Page Mode and Extended Data Out Single In-Line Memory Module pinouts, and other memory circuit designs.

Claims

1. A memory device having a plurality of memory elements, each of the elements having an associated address, the memory device further comprising:

addressing circuitry adapted to receive at least a first portion of an address from a source external to the memory device in response to a transition of an address strobe signal, and further adapted to advance the address in a predetermined address sequence in response to a subsequent transition of the address strobe signal; and

output buffer circuitry adapted to drive data from the memory device only after a plurality of transitions of the address strobe signal in a burst read access.

2. The memory device of claim 1, wherein:

said output buffer circuitry is further adapted to switch between a logic low data value and a logic high data value in response to a single transition of the address strobe signal.

3. The memory device of claim 1, wherein:

said output buffer circuitry is further adapted to drive a logic low data value from the device after a falling edge of the address strobe signal, and then to drive a logic high data value from the device after a rising edge of the address strobe signal.

4. A memory device having a plurality of memory elements, each of the elements having an associated address, the memory device further comprising:

addressing circuitry adapted to provide a series of addresses in a burst mode of operation; and

a write enable signal node for receiving a write enable signal which is adapted to select between read and write cycles of the memory device, wherein a burst access of the memory device is terminated in response to a transition of the write enable signal.

5. A memory device having an address latch node for receiving an address strobe signal, an address latch for receiving at least a portion of a first memory address and an array of memory elements, the memory device comprising:

an address generating circuit responsive to the address strobe signal and to an output of the address latch for generating a second memory address, wherein the second memory address is used to access the array; and

an output circuit in electrical communication with the address latch node for driving data received from the array, out of the memory device after a plurality of transitions of the address strobe signal.

6. The memory device of claim 5, wherein:

said output circuit is adapted to drive data out of the memory device after a programmable number of transitions of the address strobe signal.

7. The memory device of claim 5, further comprising:

an output enable signal node for receiving an output enable signal for enabling data to be driven from the memory device; and

means for performing burst read and burst write access cycles while said output enable signal node is connected to a supply potential node which defines a state of the output enable signal for enabling data to be driven.

8. The memory device of claim 5, wherein said address latch receives a column portion of the first address, the memory device further comprising:

a row address strobe signal node for receiving a row address strobe signal;

a row address latch coupled to said row address strobe signal node for latching a row address in response to the row address strobe signal;

a control signal node for receiving a control signal; and

a mode control latch in electrical communication with said control signal node and said row address strobe signal node, for latching a state of the control signal upon a transition of the row address strobe signal, wherein the state is used to select between a burst mode and a nonburst mode of the memory device.

9. The memory device of claim 8 wherein:

said control signal node is a write cycle enable signal node.

10. The memory device of claim 5, wherein:

said address generating circuit latches a first column address in response to a first transition of the address strobe signal, and advances the first column address to generate a second column address in response to a second transition of the address strobe signal.

11. The memory device of claim 5, wherein:

said address latch comprises a transparent latch.

12. A memory device having an address strobe signal node for receiving an address strobe signal and an array of memory elements, the memory device comprising:

an address latch responsive to a first transition of the address strobe signal to latch at least a portion of a first initial memory address into the memory device;

an address generating circuit adapted to generate a series of burst addresses which are determinable from the first initial memory address, wherein each of the burst addresses is generated in response to a corresponding transition of the address strobe signal; and

a control circuit in electrical communication with said address latch and the address strobe signal node for enabling said address latch to latch at least a portion of a second initial address into the memory device in response to the address strobe signal after a predetermined number of burst access cycles have occurred.

13. The memory device of claim 12, wherein:

the predetermined number of burst access cycles is a programmable number.

14. The memory device of claim 12, further comprising:

a write enable signal node for receiving a write enable signal, wherein a burst access of the memory device is interrupted in response to a transition of the write enable signal.

15. A memory device having a plurality of data nodes for receiving and driving a plurality of data signals, an array of memory elements, and a plurality of address nodes for receiving a row and a column address, the memory device comprising:

a row address strobe node for receiving a row address strobe signal for latching the row address in the memory device;

a write control signal node for receiving a write control signal for selecting between read and write accesses of the memory device; and

first and second column address strobe nodes for receiving first and second column address strobe signals, wherein either of said first and second column address strobe signals latch the column address, and either of said first and second column address strobe signals being active during a read access of the memory device will enable data to be driven on each of the data nodes, and only a first plurality of the data signals will be stored in the array in response to said write control signal selecting a write access and said first column address strobe node being active and said second column address strobe node being inactive.

16. A memory device having an array of memory elements, in which a row address has been selected, comprising:

a means of selecting a first column address and accessing an element of the array of memory elements at the row and first column address, in response to a transition of a column address strobe signal; and

a means for modifying the first column address within the memory device to provide a second column address and for accessing a further element of the array, in response to the column address strobe signal;

an output buffer to provide output data from the memory device only after a plurality of transitions of the column address strobe signal in a burst read access; and

a control circuit responsive to a write enable signal to terminate a burst access of the memory device.

17. The memory device according to claim 16, further comprising:

a burst mode enable means for enabling a burst mode of operation of the memory device.

18. The memory device according to claim 16, further comprising:

a means for disabling a burst mode of operation of the memory device.

19. The memory device according to claim 18, further comprising:

a mode control latch for latching a mode of operation of the memory device when the row address is selected.

20. The memory device according to claim 16, further comprising:

a row address strobe signal node for receiving a row address strobe signal to select the row address;

a write enable input node for receiving the write enable signal; and

a mode control latch circuit coupled to said write enable input node and at least one of said address signal input nodes for latching a mode of operation of the memory device in response to an active state of the write enable signal when the row address strobe signal is activated subsequent to the column address strobe signal being activated.

21. A memory device having external nodes for receiving a plurality of signals consisting essentially of a column address strobe signal a cycle of which defines an access cycle period, a row address strobe signal, a write enable signal, an output enable signal, address signals, data signals and power supply signals, the memory device comprising:

means for performing a burst write access of a first plurality of memory elements in response to a first address and a first plurality of transitions of the column address strobe signal, and for performing a burst read access of a second plurality of memory elements in response to a second address and a second plurality of transitions of the column address strobe signal, wherein a transition of the write enable signal will terminate a burst access of the memory device.

22. The memory device according to claim 21, further comprising:

a data output circuit for driving data from the memory device in the burst read access , wherein a first data signal from a third plurality of memory elements is driven from the memory device in a next burst read access subsequent to a last data signal of the second plurality of memory elements being driven from the memory device, providing for a continuous series of burst read memory cycles.

23. A method of reading data from a memory device having an address latch, an address counter, an address strobe node for receiving a column address strobe, an output data driver and an array of memory elements, the method comprising:

applying a first column address strobe to the address strobe node for latching a first column address;

accessing a first memory element of the array of memory elements at the first column address;

applying a second column address strobe to the address strobe node for advancing the column address within the memory device to specify a second column address;

accessing a second memory element of the array of memory elements at the second column address;

switching data driven to an external data node from a logic low level to a logic high level in response to a single transition of the column address strobe; and

maintaining a high impedance state on the output data driver at least until said step of applying the second column address strobe.

24. The method of reading data from a memory device according to claim 23, further comprising:

applying a third column address strobe to the address strobe node for advancing the column address to specify a third column address; and

latching an output of the memory device from the first column address in synchronization with the third column address strobe.

25. The method of reading data from a memory device according to claim 23, further comprising:

selecting a burst mode of operation of the memory device prior to said applying the first column address strobe.

26. A method of terminating a burst access of a memory device having an array of memory elements, an address generation circuit for providing a plurality of addresses for accessing the array, and a read and write cycle input node for receiving a write enable signal, the method comprising:

toggling the write enable signal during the burst access.

27. The method according to claim 26, further comprising:

resetting a burst length counter in response to said toggling the write enable signal during the burst access.

28. A Single In Line Memory Module comprising:

a memory device having an array of memory elements, each of the memory elements having an associated address;

a plurality of address lines coupled to said memory device; and

an address strobe signal line electrically coupled to said memory device, wherein said memory device is responsive to an address strobe signal received on said address strobe signal line to latch an address within said memory device from said plurality of address lines, and said memory device is responsive to a transition of the address strobe signal received on said address strobe signal line to advance the address within said memory device in a predetermined sequence.

29. The Single In Line Memory Module according to claim 28, wherein said memory chip further comprises:

a data node for driving data from the Single In Line Memory Module, wherein driven data is switched from a first data value to a second data value in response to a single transition of the address strobe signal.

30. The Single In Line Memory Module according to claim 29, wherein:

a first transition of the address strobe signal is used to latch a first address within the memory device; and

the first data value from the first address of the memory device is driven from said data node in response to a second transition of the address strobe signal.

31. The Single In Line Memory Module according to claim 28, further comprising:

a means for inhibiting the address strobe signal from advancing the address.

32. The Single In Line Memory Module according to claim 28, further comprising:

a write cycle control line for selecting a write access of said memory chip when a write enable signal on said write cycle control line is active at a time when said address strobe signal line latches the address, and for terminating a burst access of said memory chip.

33. The Single In Line Memory Module according to claim 28, wherein the memory chip further comprises an output enable signal node coupled to a ground potential node of the Single In Line Memory Module.

34. A Memory Module comprising:

a memory device;

a plurality of address signal lines coupled to said memory device to provide an address to said memory device;

an address strobe signal line coupled to said memory device; and

an address generation circuit within said memory device, coupled to said address strobe signal line, for receiving and advancing the address, to provide multiple data accesses of said memory device in synchronization with multiple transitions of an address strobe signal on said address strobe signal line after only one address is received.

35. The Memory Module according to claim 34, further comprising:

a control signal line; and

a write enable signal line used in combination with said address strobe signal line for selecting between read and write data accesses of said memory device, and used in combination with said control signal line for selecting between a synchronous burst access cycle and an asynchronous nonburst access cycle of said memory device.

36. The Memory Module according to claim 34, further comprising:

a write enable signal line for receiving a write enable signal, wherein a transition of said write enable signal on said write enable signal line during a burst access cycle terminates the burst access cycle.

37. The Memory Module according to claim 34, further comprising:

at least one data node for transferring data to and from the memory module, wherein data from the memory module transitions from a first data value to a second data value in response to a single transition of the signal on said address strobe signal line and data is driven from the memory module only after a plurality of transitions of the signal on said address strobe signal line in a burst read access of the memory module.

38. A computer system which is capable of rapid storage and retrieval of data, comprising:

a microprocessor; and

a memory circuit adapted to store and retrieve data in a burst access in response to a memory address received from said microprocessor and in response to an address strobe signal, wherein said memory circuit is adapted to latch the memory address and perform a first memory access in response to a first transition of the address strobe signal within the burst access and is further adapted to generate an additional memory address and perform a memory access cycle in response to each of a plurality of additional transitions of the address strobe signal within a burst access.

39. The computer system of claim 38, wherein data read from the memory address of said memory circuit is provided by said memory circuit to said microprocessor after at least two transitions of the address strobe signal in the burst access.

40. The computer system of claim 39, wherein additional data values from a predetermined sequence of addresses of said memory circuit are provided to said microprocessor in response to additional transitions of the address strobe signal after said microprocessor receives data from the memory address.

41. The computer system of claim 38, wherein said memory circuit comprises dynamic random access memory elements.

42. A computer system comprising:

a microprocessor that provides an address; and

a memory device containing data at a location corresponding to the address, said memory providing burst access in response to the address, wherein burst access comprises;

a plurality of periods, a column address strobe signal being received by said memory each period;

a column address portion, of the address, being received by said memory device only in a first period of the plurality of periods in response to the column address strobe signal; and

the data at the location corresponding to the address is provided at an output of said memory device after at least two periods.

43. The computer system of claim 42, wherein said memory device is attached to a single in line memory module.

44. The computer system of claim 42, wherein the column address strobe signal is provided to said memory device from the computer system in synchronization with a system clock signal.

45. A computer system which is capable of rapid storage and retrieval of data, comprising:

a microprocessor; and

a burst extended data out memory device to store and retrieve data in a burst access in response to a memory address received from said microprocessor and in response to an address strobe signal, whereby said burst extended data out memory device is operative to latch the memory address and perform a first memory access in response to a first transition of the address strobe signal within the burst access and is further operative to generate an additional memory address and perform a memory access cycle in response to each of a plurality of additional transitions of the address strobe signal within the burst access.

46. The computer system of claim 45, wherein the burst access is terminated in response to a transition of a write enable signal received by said burst extended data out memory device.

47. A burst access memory device comprising:

an array of memory elements;

a column addressing circuit coupled to said array of memory elements, responsive to a column address strobe signal to generate a series of column addresses in a burst access of the memory device;

wherein the burst access memory device is responsive to a transition of a write cycle control signal to terminate the burst access.

48. The burst access memory device of claim 47, wherein data from said burst access memory device is driven from said burst access memory device only after at least two high to low transitions of the column address strobe signal in a burst read access.

49. The burst access memory device of claim 48, further comprising:

an output enable node adapted to receive an output enable signal; and

a data output node;

wherein data from the burst access memory device becomes valid at the data output node within a predetermined period after a high to low transition of the column address strobe signal in the burst read access while the output enable signal is active.