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Method for circuit verification and multi-level circuit optimization based on structural implications

  • US 5,526,514 A
  • Filed: 06/21/1994
  • Issued: 06/11/1996
  • Est. Priority Date: 06/21/1994
  • Status: Expired due to Fees
First Claim
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1. A method for verifying that a first logic circuit is equivalent to a second logic circuit, the first logic circuit having a first plurality of inputs and a first plurality of internal nodes and the second logic circuit having a second plurality of inputs and a second plurality of internal nodes, the method comprising the steps of:

  • a) coupling the first plurality of inputs to the second plurality of inputs;

    b) assigning a first combination of signal values to a combination of at least one of the first plurality of internal nodes, such that the corresponding assignment creates an unjustified signal in said node;

    c) determining, through logic implications, signal values for the first plurality and second plurality of internal nodes not included in the combination of some or all the first plurality of internal nodes such that the signal values result in conditions which are consistent with the first combination of signal values in the the combination of at least one of the first plurality of internal nodes;

    d) extracting a resulting combination of signal values from a second combination of at least one of the second plurality of internal nodes corresponding to the first combination signal values;

    e) storing the resulting combination of signal values in an internal memory;

    f) repeating the steps of assigning, determining, extracting and storing for a different combination of at least one of the first plurality of internal nodes of the first and the second circuit to create a list of indirect implications; and

    g) using the list of indirect implications to verify that the first and second circuits are equivalent based on a set of pre-stored signal relationships in the internal memory.

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