High-density DRAM structure on soi
First Claim
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1. An integrated circuit cell for dynamic random access memories, comprising in combination:
- a silicon-on-oxide wafer comprised of an oxide layer on a surface of an underlying support wafer and a patterned silicon source layer on a surface of said oxide layer;
a capacitor trench extending through said silicon source layer and said oxide layer and into said underlying support wafer;
a first capacitor plate layer formed conformally on a wall of said capacitor trench, said first capacitor plate layer extending to and connected with said patterned silicon source layer;
a capacitor dielectric layer formed on said first capacitor plate layer;
a silicon channel layer formed conformally over said capacitor dielectric layer and overlying a region of said patterned silicon source layer, said silicon channel layer forming a second capacitor plate as well as a channel layer;
a polysilicon drain layer overlying said silicon channel layer in said region where said silicon channel layer overlays said silicon source layer;
a vertical opening extending through said silicon source layer, said silicon channel layer, and said polysilicon drain layer, said opening forming a wall surface in a region where the layers overlay one another, said wall surface comprising an edge surface of in each layer respectively aligned vertically along said wall surface;
a gate dielectric covering said wall surface; and
a vertical gate in said opening in contact with said gate dielectric.
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Abstract
A high density, DRAM cell array with a very short channel, vertical gate transfer transistor that can be manufactured using conventional photolithography process steps. The conventional four-by-four DRAM array shown schematically in FIG. 1a is rearranged to the shared-gate, double-bit array shown schematically in FIG. 1b. Trench storage capacitors and vertical FET transistors are arranged in pairs with a common vertical gate and a common substrate, allowing both bit and substrate contacts to be shared by adjacent cells.
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Citations
20 Claims
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1. An integrated circuit cell for dynamic random access memories, comprising in combination:
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a silicon-on-oxide wafer comprised of an oxide layer on a surface of an underlying support wafer and a patterned silicon source layer on a surface of said oxide layer; a capacitor trench extending through said silicon source layer and said oxide layer and into said underlying support wafer; a first capacitor plate layer formed conformally on a wall of said capacitor trench, said first capacitor plate layer extending to and connected with said patterned silicon source layer; a capacitor dielectric layer formed on said first capacitor plate layer; a silicon channel layer formed conformally over said capacitor dielectric layer and overlying a region of said patterned silicon source layer, said silicon channel layer forming a second capacitor plate as well as a channel layer; a polysilicon drain layer overlying said silicon channel layer in said region where said silicon channel layer overlays said silicon source layer; a vertical opening extending through said silicon source layer, said silicon channel layer, and said polysilicon drain layer, said opening forming a wall surface in a region where the layers overlay one another, said wall surface comprising an edge surface of in each layer respectively aligned vertically along said wall surface; a gate dielectric covering said wall surface; and a vertical gate in said opening in contact with said gate dielectric. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
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12. A pair of integrated circuit, shared gate, cells for dynamic random access memories, comprising in combination:
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a silicon-on-oxide wafer comprised of an oxide layer on the upper surface of an underlying support wafer and a silicon source layer on the upper surface of said oxide layer; a pair of capacitor trenches extending through said silicon source layer and said oxide layer and into said underlying support wafer; a first capacitor plate layer formed conformally on the wall of each of said pair of said capacitor trenches over said isolation oxide, said capacitor plate layer extending to and connected with said silicon source layer; a capacitor dielectric layer formed on said polysilicon capacitor plate layer; a silicon channel layer formed conformally over said capacitor dielectric layer and overlying a region of said silicon source layer, said silicon layer forming a second capacitor plate and a channel layer; a polysilicon drain layer overlying said silicon channel layer in said region where said silicon channel layer overlays said silicon source layer; a vertical opening extending through silicon source layer, said silicon channel layer, and said polysilicon drain layer forming a pair of facing vertical wall surfaces in the region where the layers overlay one another with an edge in each layer respectively aligned vertically along said pair of facing vertical wall surfaces; said silicon channel layer extending from one of said facing wall surfaces forming the channel layer and the second capacitor plate layer for one cell of said pair of integrated circuit cells and said silicon channel layer extending from the other of said facing wall surfaces forming the channel layer and the second capacitor plate layer for the other cell of said pair of integrated circuit cells; a gate dielectric covering said pair of facing vertical wall surfaces; and a vertical gate in said opening in contact with said gate dielectric. - View Dependent Claims (13, 14, 15, 16, 17, 18, 19, 20)
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Specification