Magnetic field detection

• US 5,528,067 A
• Filed: 05/08/1995
• Issued: 06/18/1996
• Est. Priority Date: 05/08/1995
• Status: Expired due to Term

• Current Assignee: Raytheon Company (Rtx Corporation)
• Original Assignee: Hughes Aircraft Company (Rtx Corporation)
• Inventors: Farb, Joseph E.
• Primary Examiner(s): MINTEL, WILLIAM A
• Application Number:
  US08/438,132
• Time in Patent Office: 407 Days
• Field of Search: 257/421, 257/422, 257/426, 257/425, 257/424, 257/401, 257/365, 257/366, 257/347, 73/DIG. 2, 73/DIG. 1, 73/DIG. 3, 73/DIG. 4, 73/514.16, 324/252
• US Class Current: 257/401
• CPC Class Codes: G01R 33/07 Hall effect devices
• CPC Class Codes: Y10S 73/02 Magnetostrictive

Abstract

A solid state triode employs the Hall effect to asymmetrically proportion flow of current through different branches of a number of cascaded bifurcated N- charge carrier channels (10,18,20), thereby providing an indication of strength and direction of an applied magnetic field by measuring magnitude and sense of the difference between currents flowing in the two channel branches (14,16,24,26,30,32). The solid state triode is formed on an silicon-on-insulator (SOI) substrate (47,48,49) in which an N+ source region (54) and at least two end N+ drain regions (56,58) are interconnected by an N- charge carrier channel (60) that is defined by a plurality of P+ regions (64a,64b,64c,64d) in a thin single crystal silicon substrate (49) between the source and drain regions (54,56,58). A polysilicon gate (52) overlies the N- channel and acts as a self-aligning mask during manufacture of the triode to precisely align the N+ and P+ doping to the polysilicon gate configuration. The SOI has a very thin N- doped layer to which the N+ and P+ doping is applied in steps of successively different energy levels so that the doping extends completely through the N- layer and is uniform throughout the thickness of the layer. The N- channel is narrow and has a width at least twice the thickness of the crystal silicon uppermost layer of the SOI substrate.

Claims

1. A semi-conductor device comprising:

a substrate comprising a single crystal silicon layer of N- type and having a thickness of 0.3 to 0.5 microns;

a first region of N+ type on said substrate;

second and third regions of said N+ type on said substrate and spaced from each other and from said first region;

a fourth region of P+ type on said substrate interposed between said first region and said second and third regions and defining a bifurcated channel of said N+ type extending from said first region to each of said second and third regions; and

conductive elements connected to said regions.

2. The semi-conductor device of claim 1 wherein said fourth region comprises a plurality of mutually discrete channel defining regions spaced from one another and defining said bifurcated channel, said bifurcated channel comprising a depleted space charge channel extending between said first region and said second and third regions.

3. The semi-conductor device of claim 1 including an elongated conductive gate overlying and indirectly delineating said bifurcated channel.

4. The semi-conductor device of claim 3 wherein said fourth region extends along and delineates said bifurcated channel, and wherein said elongated conductive gate has a configuration delineating said regions and thereby indirectly delineating said bifurcated channel.

5. The semi-conductor device of claim 1 wherein said substrate comprises a body of silicon-on-insulator (SOI) having said single crystal silicon layer, said fourth region being formed in said single crystal silicon layer and being substantially uniformly doped throughout the thickness of said single crystal silicon layer.

6. The semi-conductor device of claim 1 further comprising a gate oxide overlying said single crystal silicon layer, and an electrically conductive gate on said gate oxide layer overlying said bifurcated channel.

7. The semi-conductor device of claim 6 wherein said electrically conductive gate is bifurcated and generally configured the same as said bifurcated channel, said electrically conductive gate having enlarged end portions overlying said first, second and third regions and having openings in said enlarged end portions that are substantially coextensive with said first, second and third regions, respectively.

8. The semi-conductor device of claim 6 wherein said N- layer is uniformly doped throughout the thickness of said single crystal silicon layer, and wherein said fourth region is uniformly doped throughout the thickness of said single crystal silicon layer, said fourth region having mutually spaced adjacent sections defining an N- depleted space charge channel between said sections extending from said first region to said second and third regions and underlying said electrically conductive gate.

9. The semi-conductor device of claim 8 wherein said single crystal silicon layer has a thickness of about 0.3 microns, and wherein said depleted space charge channel has a uniform width of about 2 microns.

10. A solid state magnetic field detector comprising;

a substrate having a source region, and first and second drain regions spaced from each other and from said source region, wherein said substrate comprises a silicon-on-insulator body having a silicon layer with a thickness of 0.3 to 0.5 microns and being doped with a first type of impurity at a first doping level, and said source and drain regions comprise areas of said silicon layer doped with said first type of impurity at a second doping level which is higher than said first doping level; and

a bifurcated charge carrier channel connecting said source region with each of said drain regions wherein said silicon layer is doped with a second type of impurity along and on opposite sides of said channel.

11. The solid state magnetic field detector of claim 10 including a gate overlying and coextensive with said channel, and electric potential conductors connected to said gate and to said source and drain regions.

12. The solid state magnetic field detector of claim 10 including a current difference detecting circuit connected to said drain regions.

13. The solid state magnetic field detector of claim 10, wherein said substrate is of a first type and includes a plurality of regions of a second type delineating said channel.

14. The solid state magnetic field detector of claim 10 wherein said silicon layer is doped with said second type of impurity uniformly from top to bottom of said silicon layer.

15. The solid state magnetic field detector of claim 10 wherein said channel has a uniform width.

16. The solid state magnetic field detector of claim 10 wherein said channel extends completely through said lightly doped silicon layer.

17. The solid state magnetic field detector of claim 16 wherein said channel has a width not less than about twice the thickness of said silicon layer which is doped at said first doping level.

18. The solid state magnetic field detector of claim 17 wherein said channel has a width not greater than about 10 microns.

19. The solid state magnetic field detector of claim 10 wherein said substrate includes a layer of N- material, said source and drain regions comprising N+ regions, and including a plurality of P+ regions in said silicon layer interposed between said N+ regions and configured to define said channel as an N- channel between said P+ regions.

20. The solid state magnetic field detector of claim 19 wherein said layer of N- material and said P+ regions are uniformly doped for the entire thickness of said silicon layer.

21. The solid state magnetic field detector of claim 20 including a conductive gate overlying said channel, and contacts on said regions and said gate for applying electrical potential.

22. The solid state magnetic field detector of claim 10 wherein said bifurcated charge carrier channel has a base leg connected at a common junction to first and second branch legs, and including second and third bifurcated charge carrier channels connected respectively with said first and second branch legs, said first drain region and a third drain region being connected to said second bifurcated channel and said second drain region and a fourth drain region being connected to said third bifurcated channel.