Thin film chip capacitor for electrical noise reduction in integrated circuits

• US 5,528,083 A
• Filed: 10/04/1994
• Issued: 06/18/1996
• Est. Priority Date: 10/04/1994
• Status: Expired due to Fees

• Current Assignee: Sun Microsystems Incorporated (Oracle Corporation)
• Original Assignee: Sun Microsystems Incorporated (Oracle Corporation)
• Inventors: Bogatin, Eric L., Zand, Bahram, Malladi, Deviprasad
• Primary Examiner(s): Limanek, Robert P.
• Assistant Examiner(s): Hardy, David B.
• Application Number:
  US08/317,900
• Time in Patent Office: 623 Days
• Field of Search: 257/784, 257/786, 257/916, 257/723, 257/924
• US Class Current: 257/786
• CPC Class Codes: H01L 2223/6611 Wire connections
• CPC Class Codes: H01L 2224/04042 Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
• CPC Class Codes: H01L 2224/05552 in top view
• CPC Class Codes: H01L 2224/05553 being rectangular
• CPC Class Codes: H01L 2224/05554 being square
• CPC Class Codes: H01L 2224/05624 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/45144 Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48245 the item being metallic
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48253 connecting the wire to a potential ring of the item
• CPC Class Codes: H01L 2224/48472 the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
• CPC Class Codes: H01L 2224/48624 Aluminium (Al) as principal constituent
• CPC Class Codes: H01L 2224/49175 Parallel arrangements
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 23/49589 Capacitor integral with or on the leadframe
• CPC Class Codes: H01L 23/50 for integrated circuit devices, e.g. power bus, number of leadsH01L23/482 - H01L23/498 take precedence
• CPC Class Codes: H01L 23/642 Capacitive arrangements H01L23/49589, H01L23/645, H01L23/647, H01L23/66 take precedence; capacitive effects between wiring layers on the semiconductor body H01L23/5222
• CPC Class Codes: H01L 24/06 of a plurality of bonding areas
• CPC Class Codes: H01L 24/45 : of an individual wire connector
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/49 : of a plurality of wire connectors
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01014 : Silicon [Si]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/07802 : not being an ohmic electrical conductor
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19107 : off-chip wires
• CPC Class Codes: H01L 2924/30107 : Inductance
• CPC Class Codes: Y10S 257/924 : with passive device, e.g. capacitor, or battery, as integral part of housing or housing element, e.g. cap

Abstract

An integrated circuit chip and flat capacitor assembly are connected with short bonding wires to reduce electrical noise. A flat chip capacitor is coupled to the chip and includes a first electrode, a second electrode and a dielectric layer disposed between the electrodes. The ground and power bonding pads of an integrated circuit chip are coupled to a number of terminals arranged in a row near the outer edge of the capacitor, where each of the terminals is coupled to one of the electrodes. The terminals of the capacitor are connected to a number of package leads of a lead frame or a other integrated circuit package. The invention includes embodiments in which the chip is placed on top of the capacitor, the capacitor is placed on top of the chip, and a flex circuit of a micro ball grid array is placed on a capacitor which is positioned on a chip.

Claims

1. An apparatus comprising:

an integrated circuit chip having a circuit and one bonding pad coupled to the circuit, wherein the integrated circuit chip includes a first chip surface and a second chip surface;

a package lead electrically coupled to the bonding pad for providing a communication path between the circuit via the bonding pad and the lead to a communication location external the integrated circuit chip; and

a capacitor electrically coupled between the package lead and the bonding pad on the integrated circuit chip, the capacitor including a first electrode and a second electrode, wherein the first electrode of the capacitor includes an electrode surface, at least a portion of the electrode surface contacting the second chip surface, wherein the electrode surface has a greater surface area than the second chip surface.

2. The apparatus of claim 1, wherein the capacitor further comprises a first terminal coupled to a first electrode of the capacitor and a second terminal coupled to a second electrode of the capacitor.

3. The apparatus of claim 2, wherein the bonding pad on the chip is coupled to the first terminal of the capacitor.

4. The apparatus of claim 3, wherein the capacitor further comprises a third terminal coupled to the first electrode and a fourth terminal coupled to the second electrode.

5. The apparatus of claim 4, wherein the bonding pad on the chip is coupled to the first terminal of the capacitor and the package lead is coupled to the third terminal of the capacitor.

6. The apparatus of claim 4, wherein the bonding pad on the chip is coupled to the second terminal of the capacitor and the package lead is coupled to the fourth terminal of the capacitor.

7. The apparatus of claim 2, wherein the bonding pad of the integrated circuit chip is coupled to the second terminal of the capacitor.

8. The apparatus of claim 2, wherein the package lead is coupled to the first terminal of the capacitor.

9. The apparatus of claim 2, wherein the package lead is coupled to the second terminal of the capacitor.

10. The apparatus of claim 2, wherein the integrated circuit chip includes a plurality of bonding pads coupled to the circuit such that the one bonding pad is included within the plurality of bonding pads, a plurality of first terminals coupled to the first electrode, a plurality of second terminals coupled to the second electrode, and a plurality of package leads coupled to the plurality of bonding pads.

11. The apparatus of claim 10, wherein each bonding pad of said plurality of bonding pads has one electrical contact with one of the plurality of said package leads.

12. The apparatus of claim 11, further comprising a flex circuit positioned adjacent a surface of the capacitor, the flex circuit including a plurality of ball contacts electrically coupled between the plurality of said package leads and the communication location external to the chip.

13. The apparatus of claim 11 wherein the plurality of said first and second terminals of the capacitor are alternately coupled to the first electrode and the second electrode.

14. The apparatus of claim 11 wherein the bonding pads include ground bonding pads and power bonding pads, and wherein only the ground bonding pads and the power bonding pads are connected to the plurality of said first terminals and plurality of said second terminals of the capacitor.

15. The apparatus of claim 2 wherein the bonding pad is coupled to one of the first terminal and the second terminal of the capacitor by a bonding wire.

16. The apparatus of claim 15 wherein the package lead is a bonding finger included in a lead frame.

17. The apparatus of claim 1 wherein the capacitor is coupled to the integrated circuit chip by an elastomer layer.

18. The apparatus of claim 1 wherein the first electrode and the second electrode each have a length, a width, and a thickness, and wherein the length and width of the first electrode and the second electrode are substantially equal.

19. A method for providing a semiconductor chip and capacitor assembly, the method comprising the steps of:

providing an integrated circuit chip having a circuit, a bonding pad coupled to the circuit, a first chip surface, and a second chip surface;

electrically coupling a package lead to the bonding pad to provide a communication path between the circuit via the bonding pad and the lead to a communication location external to the integrated circuit chip; and

electrically coupling a capacitor between the package lead and the bonding pad on the integrated circuit chip, the capacitor including an capacitor surface, at least a portion of the capacitor surface contacting the second chip surface, wherein the capacitor surface has a greater surface area than the second chip surface.

20. A method as recited in claim 19 wherein said capacitor includes a plurality of electrodes, wherein the capacitor surface is a surface of one of the electrodes, and wherein the step of coupling a capacitor includes coupling a capacitor having a terminal coupled to one of the plurality of said electrodes.

21. A method as recited in claim 20, wherein the terminal of the capacitor is coupled to the bonding pad on the chip.

22. The method of claim 19, further comprising a step of providing a flex circuit positioned adjacent a surface of the capacitor, the flex circuit including a plurality of ball contacts electrically coupled between the package lead and the communication location external to the chip.

23. The method claim 19 wherein the capacitor is coupled to the bonding pad by a bonding wire.

24. The method of claim 23 wherein said step of coupling a package lead includes coupling a bonding finger included in a lead frame to provide the communication path between the circuit and the communication location external to the integrated circuit chip.

25. An apparatus comprising:

an integrated circuit chip having a circuit and including a plurality of bonding pads coupled to the circuit;

a plurality of package leads coupled to the plurality of bonding pads for providing a communication path between the circuit via the plurality of bonding pads and the plurality of leads to a communication location external the integrated circuit chip, wherein each bonding pad of said plurality of bonding pads has one electrical contact with one of the plurality of said package leads;

a capacitor coupled between the plurality of package leads and the plurality of bonding pads on the integrated circuit chip, wherein the capacitor is physically positioned adjacent to a surface of the integrated circuit chip; and

a flex circuit positioned adjacent a surface of the capacitor, the flex circuit including a plurality of contacts electrically coupled between the plurality of said package leads and the communication location external to the chip.

26. The apparatus of claim 25 wherein the plurality of contacts included in the flex circuit are ball contacts.

27. The apparatus of claim 26 wherein the capacitor is coupled to the integrated circuit chip by an elastomer layer.

28. The apparatus of claim 25 wherein the flex circuit includes a micro ball grid array.

29. A method for providing a semiconductor chip and capacitor assembly, the method comprising the steps of:

providing an integrated circuit chip having a circuit and one bonding pad coupled to the circuit;

coupling a package lead to the bonding pad to provide a communication path between the circuit via the bonding pad and the lead to a communication location external to the integrated circuit chip;

coupling a capacitor between the package lead and the bonding pad on the integrated circuit chip, the capacitor being provided adjacent to a side of the chip; and

providing a flex circuit positioned adjacent to a surface of the capacitor, the flex circuit including a ball contact electrically coupled between the package lead and the communication location external to the chip.

30. The method of claim 29 wherein the capacitor has a smaller surface area than the integrated circuit chip.