Timing circuit for video display having a spatial light modulator

• US 5,528,317 A
• Filed: 01/27/1994
• Issued: 06/18/1996
• Est. Priority Date: 01/27/1994
• Status: Expired due to Term

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Doherty, Donald B., Gove, Robert J.
• Primary Examiner(s): Metjahic, Safet
• Application Number:
  US08/188,266
• Time in Patent Office: 873 Days
• Field of Search: 348/786, 348/715, 348/718, 348/785, 348/743, 348/742, 348/744, 348/745, 348/756, 348/759, 348/760, 348/761, 348/781, 348/503, 348/513, 348/514, 348/520, 348/551, 348/808 , 348/816, 348/196, 348/195, 348/199, 348/202, 348/536, 348/539, 345/186, 345/190, 345/185, 345/98, 345/200-202
• US Class Current: 348/743
• CPC Class Codes: H04N 9/30 using solid-state colour display devices

Abstract

A method and apparatus for synchronizing display timing in a digital television system with a pixel addressable display having a color wheel is disclosed. The display timing circuit 22 includes phase comparator 40, for comparing the phase of a wheel index signal generated by a color wheel 20 with the phase of a frame synchronization signal indicating that a complete frame is ready to be displayed. Display timing circuit 22 further comprises a color wheel synchronization generator 42 which generates a color wheel synchronization signal in response to a phase difference value produced by phase comparator 40. The color wheel synchronization signal is used to increase, decrease, or maintain the speed of color wheel 20 to achieve a known phase relationship between the frame synchronization signal and the wheel index signal. Display timing circuit 22 further comprises a clock generator applicable to generate a display master clock signal having a known frequency relation to the wheel index signal.

Claims

1. A method of synchronizing display timing to pixel data representing a video signal comprising the steps of:

receiving a wheel index signal identifying the position of a color wheel;

receiving a frame synchronization signal indicating that a complete video frame of said pixel data is ready to be displayed;

comparing the phase of said wheel index signal with the phase of said frame synchronization signal;

generating a color wheel synchronization signal in response to said comparing step for increasing or decreasing the speed of said color wheel to achieve a known phase relation with said frame synchronization signal;

generating a display master clock signal that controls the transfer of said pixel data to a pixel addressable display, said display master clock signal having a known frequency relation to said wheel index signal; and

generating a frame start synchronization signal indicating that the pixel addressable display should start displaying a next video frame, such that said synchronization signal is also used to generate a series of address and timing signals to cause a specific portion of said next video frame to be transferred to said pixel addressable display.

2. The method of claim 1, wherein said step of generating a color wheel synchronization signal is performed by dividing a line clock signal by an integer, the line clock signal being derived from the video line rate of the video signal.

3. The method of claim 1, further comprising the step of displaying a video picture on the pixel addressable display in response to said display master clock signal.

4. The method of claim 1, wherein said step of generating a display master clock signal is accomplished by receiving a parameter to set the frequency of the display master clock.

5. The method of claim 1, wherein said display master clock signal generated by said step of generating a display master clock signal has a known phase relation of substantial phase equality with said wheel index signal.

6. The method of claim 1, further comprising the step of transferring the pixel data from a display memory to the pixel addressable display in response to said display master clock signal.

7. A display timing circuit for synchronizing display timing to a video signal in a digital television system having a pixel addressable display and a color wheel wherein the color wheel generates a wheel index signal identifying the position of the color wheel, comprising:

a phase comparator for comparing the phase of said wheel index signal with the phase of a frame synchronization signal indicating that a complete video frame in the video signal is ready to be displayed, thereby generating a phase difference value;

a color wheel synchronization signal generator for generating a color wheel synchronization signal in response to said phase difference value for increasing or decreasing the speed of the color wheel to achieve a known phase relation between said frame synchronization signal and said wheel index signal;

a dock generator for generating a display master clock signal having a known frequency relation with said wheel index signal;

a frame start signal generator operable to generate a frame start synchronization signal indicating that said display should start displaying the next video frame; and

a clock frequency generator circuit for generating an intermediate clock signal with the same frequency as said display master clock signal, and wherein said clock generator comprises a phase locked loop operable to generate said display master dock signal by locking the phase of said intermediate clock signal to the phase of said wheel index signal.

8. The display timing circuit of claim 7, wherein said color wheel synchronization signal generator comprises a divide-by-N counter for dividing a line clock signal derived from said video signal by N where N is the phase difference value.

9. The display timing circuit of claim 7, wherein said phase comparator and said clock generator are programmable, allowing said display timing circuit to be used with different sizes of pixel addressable displays and different types of video signals.

10. The display timing circuit of claim 7, further comprising:

a sequence controller for executing display sequence instructions in response to said frame start synchronization signal, thereby generating address and timing signals that cause specific segments of an output video frame stored in a display memory to be transferred to said pixel addressable display.

11. The display timing circuit of claim 7, further comprising:

a sequence controller for executing display sequence instructions in response to said frame start synchronization signal, thereby generating a series of control signals and segment signals, each segment signal denoting a specific portion of an output video frame stored in a display memory to be transferred to said pixel addressable display; and

a display control signal generator operable to generate display transfer signals upon receipt of said control signals, the display transfer signals controlling said pixel addressable display'"'"'s receipt of pixel data from said display memory.

12. The display timing circuit of claim 7, further comprising:

a sequence controller for executing display sequence instructions in response to said frame start synchronization signal, thereby generating a series of control signals and segment signals, each segment signal denoting a specific portion of an output video frame stored in a display memory to be transferred to said pixel addressable display; and

a frame ram control circuit operable to generate one or more absolute addresses in response to said series of segment signals, the absolute addresses indicating the addresses in said display memory of the pixel data corresponding to the specific portion of the output video frame to be transferred to said pixel addressable display.

13. The display timing circuit of claim 7, further comprising:

a sequence controller for executing display sequence instructions in response to said frame start synchronization signal, thereby generating a series of control signals and segment signals, each segment signal denoting a specific portion of an output video frame stored in a display memory to be transferred to said pixel addressable display; and

a timing memory for storing said display sequence instructions.

14. A digital television system having a color wheel to provide colored light to a spatial light modulator and operable to generate a wheel index signal identifying the position of the color wheel, comprising:

a display memory operable to store output video frame pixel data;

a spatial light modulator display; and

a display timing circuit comprising;

a phase comparator for comparing the phase of said wheel index signal with the phase of a frame synchronization signal indicating that a complete video frame in said video signal is ready to be displayed thereby generating a phase difference value;

a color wheel synchronization signal generator for generating a color wheel synchronization signal in response to said phase difference value for increasing or decreasing the speed of said color wheel to achieve a known phase relation between said frame synchronization signal and said wheel index signal;

a clock generator for generating a display master dock signal having a known frequency relation with said wheel index signal and used to control the transfer of output video frame pixel data to said spatial light modulator;

a frame start signal generator operable to generate a frame start synchronization signal indicating that said spatial light modulator should begin displaying the next video frame; and

a sequence controller for executing display sequence instructions in response to said frame start synchronization signal thereby generating a series of address and timing signals, said series of address and timing signals capable of causing a specific portion of an output video frame stored in a display memory to be transferred to the pixel addressable display.

15. The digital television system of claim 14, wherein said spatial light modulator comprises a digital micro-mirror device.