Calibration circuit for capacitive sensors
First Claim
1. A circuit for calibrating a capacitive sensor having two inputs and an output comprising:
- a memory storing at least two digital calibration codes;
a first switch means connected to said memory for switching between said two code portions;
a digital-to-analog converter having an input, said input having a first selectable connection so that when said first selectable connection is in a first state, said digital-to-analog converter is connected to said first switch and when said first selectable connection is in said second state, said digital-to-analog converter is connected to a code mirror circuit, said digital-to-analog converter having an output with a second selectable connection to one of said inputs of said sensor;
said code mirror circuit converting said calibration code to a predetermined digital mirror code; and
a first voltage source having a third selectable connection between one of said two inputs of said sensor;
wherein said first voltage source and said output of said digital-to-analog converter are alternately connected to opposite inputs of said sensor.
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Accused Products
Abstract
A calibration circuit for a capacitive sensor is disclosed which compensates for any offsets or sensitivity variations of the sensor once the sensor has been calibrated. The circuit uses digital calibration codes determined during calibration. The digital codes are modified and unmodified as inputs to a digital-to-analog converter. The digital-to-analog converter applies the corresponding analog equivalents to the inputs of the sensor in a alternate manner so that the voltages applied to the sensor are balanced around a mirror voltage. The balance around the mirror voltage reduces the electrostatic deflection of the sensor which reduces sensor errors. The output of the sensor is converted to a pulse density signal representative of the output of the sensor.
32 Citations
17 Claims
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1. A circuit for calibrating a capacitive sensor having two inputs and an output comprising:
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a memory storing at least two digital calibration codes; a first switch means connected to said memory for switching between said two code portions; a digital-to-analog converter having an input, said input having a first selectable connection so that when said first selectable connection is in a first state, said digital-to-analog converter is connected to said first switch and when said first selectable connection is in said second state, said digital-to-analog converter is connected to a code mirror circuit, said digital-to-analog converter having an output with a second selectable connection to one of said inputs of said sensor; said code mirror circuit converting said calibration code to a predetermined digital mirror code; and a first voltage source having a third selectable connection between one of said two inputs of said sensor; wherein said first voltage source and said output of said digital-to-analog converter are alternately connected to opposite inputs of said sensor. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
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12. A circuit for calibrating a capacitive sensor having two inputs and an output comprising:
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a memory storing at least two digital calibration codes; a clock; a first switch connected to said memory for switching between said two code portions; a digital-to-analog converter having an input, said input having a second switch so that when said second switch is in a first state, said digital-to-analog converter is connected to said first switch and when said second switch is in said second state, said digital-to-analog converter is connected to a code mirror circuit, said digital-to-analog converter having an output with a third switch connected to one of said inputs of said sensor; said code mirror circuit converting said calibration code to a predetermined digital mirror code; a first voltage source having a fourth switch between one of said two inputs of said sensor; an integrator having a feedback loop including a fifth switch and a capacitor; a comparator connected to said integrator outputting a pulse density modulated signal; and wherein each of said second, third, fourth and fifth switches are connected to said clock for operating said second, third, fourth and fifth switches synchronously between a first state and a second state. - View Dependent Claims (13, 14, 15, 16, 17)
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Specification