Nonvolatile semiconductor memories with a cell structure suitable for a high speed operation and a low power supply voltage

• US 5,528,537 A
• Filed: 07/21/1995
• Issued: 06/18/1996
• Est. Priority Date: 03/31/1993
• Status: Expired due to Term

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Cho, Sung-Hee, Lee, Hyong-Gon, Hwang, Sang-Ki, Jang, Cheol-Ung, Ko, Young-Wi
• Primary Examiner(s): Nelms, David C.
• Assistant Examiner(s): DINH, SON T
• Application Number:
  US08/505,038
• Time in Patent Office: 333 Days
• Field of Search: 365/185, 365/230.03, 365/185.11
• US Class Current: 365/185.11
• CPC Class Codes: G11C 17/123 comprising cells having several storage transistors connected in series
• CPC Class Codes: H10B 20/00 Read-only memory [ROM] devices
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

A nonvolatile semiconductor memory with a unit cell structure suitable for high speed operation and a low power supply voltage. The nonvolatile semiconductor memory includes a switching circuit including block select transistors connected by its respective terminal to a corresponding bit line. This switching circuit transmits a signal only when a string to which the switching circuit corresponds is selected. A second active region having a different impurity concentration from a first active region constituting source and drain regions of memory transistors is formed at a substrate contact portion of a bit line contact portion where the memory string and bit line are connected. The impurity concentration of the second active region is lower than that of the first active region.

Claims

1. A NAND type nonvolatile semiconductor memory, comprising:

a plurality of bit lines;

a plurality of NAND type unit memory cells for storing memory data, each said plurality of NAND type unit memory cells including at least one memory transistor for selectively accessing desired memory data, wherein;

said plurality of NAND type unit memory cells being arranged in a plurality of strings, each of said plurality of strings including a subplurality of said plurality of NAND type unit memory cells,

each of said plurality of bit lines being connected to at least two of said plurality of strings, and

said plurality of bit lines being

arranged into a plurality of blocks;

a plurality of string select transistors including at least one depletion mode transistor connected to each of said plurality of strings, said plurality of string select transistors selecting one of said at least two of said plurality of strings connected to each of said plurality of bit lines in response to a string select signal; and

a plurality of block select transistors connected respectively to each of said plurality of strings for selecting a respective one of said plurality of blocks in response to a block select signal.

2. The NAND type semiconductor memory of claim 1, further comprising:

means for generating said block select signal from a row address to select said respective one of said plurality of blocks containing desired memory data.

3. The NAND type semiconductor memory of claim 1, wherein:

each of said plurality of block select transistors is an enhancement mode transistor.

4. A NAND type nonvolatile semiconductor memory, comprising a plurality of bit lines arranged into a plurality of blocks, each of said plurality of blocks comprising:

a bit line;

a first block transistor connected to said bit line;

a second block transistor connected to said bit line;

a first plurality of string select transistors including at least one depletion mode transistor connected in series and to said first block transistor;

a second plurality of string select transistors connected in series and to said second block transistor;

a first plurality of NAND type unit memory cells connected in series and to said first plurality of string select transistors; and

a second plurality of NAND type unit memory cells connected in series and to said second plurality of string select transistor;

said first block transistor, said first plurality of string select transistors, and said first plurality of NAND type unit memory cells being connected in series in a first string;

said second block transistor, said second plurality of string select transistors, and said second plurality of NAND type unit memory cells being connected in series in a second string;

said first plurality of string select transistors selecting said first plurality of NAND type unit memory cells, in response to a first string select signal; and

said second plurality of string select transistors selecting said second plurality of NAND type unit memory cells, in response to a second string select signal.

5. The NAND type semiconductor memory of claim 4, wherein each of said plurality of blocks further comprise:

means for generating a unique block select signal from a row address to select memory data in said respective block.

6. The NAND type semiconductor memory of claim 4, wherein:

each of said first block select transistor and said second block select transistor is an enhancement mode transistor.