Method for manufacturing a cubically integrated circuit arrangement

• US 5,529,950 A
• Filed: 01/23/1995
• Issued: 06/25/1996
• Est. Priority Date: 02/07/1994
• Status: Expired due to Term

• Current Assignee: Qimonda AG (Infineon Technologies AG)
• Original Assignee: Siemens AG
• Inventors: Schwarzl, Siegfried, Hoenlein, Wolfgang
• Primary Examiner(s): Fourson, George
• Assistant Examiner(s): Graybill, David E.
• Application Number:
  US08/377,049
• Time in Patent Office: 519 Days
• Field of Search: 437/974, 437/170, 437/203, 437/208, 437/225, 437/974, 437/915, 204/129.3, 204/129.55, 257/686, 257/777
• US Class Current: 438/107
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV] manufacturing via connections per se H01L21/76898
• CPC Class Codes: H01L 2225/06589 Thermal management, e.g. cooling
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 25/50 Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: Y10T 29/49126 Assembling bases
• CPC Class Codes: Y10T 29/4913 Assembling to base an electrical component, e.g., capacitor, etc.

Abstract

A method used in manufacturing a cubically integrated circuit arrangement. A silicon wafer, wherein through pores are produced by electrochemical etching are insulated from the silicon wafer, and are provided with conductive fills, is secured as a carrier plate (24) to a substrate (21) that has components and that is integrated in a cubically integrated circuit arrangement. Terminal pads (25) that are electrically connected to conductive fills and that are arranged on the surface of the carrier plate (24) thereby meet contacts (23) to the components that are arranged at the surface of the substrate (21) adjoining the carrier plate (24) and that are firmly connected thereto.

Claims

1. A method for manufacturing a cubically integrated circuit arrangement, comprising the steps of:

producing through pores in a doped monocrystalline silicon wafer by electrochemical etching in a fluoride-containing, acidic electrolyte wherein the silicon wafer is connected as an anode;

at least partially providing said through pores, insulated from the silicon wafer by insulating material, with conductive fills;

securing the silicon wafer, as a first carrier plate, on a first principal surface of a first substrate, the first substrate having components at least in a region of the first principal surface, the first substrate having contacts to the components on the first principal surface; and

forming terminal pads, that are electrically connected to at least one conductive fill and that meet at least one contact on the first principal surface, on a surface of the carrier plate adjoining the first principal surface, said terminal pads being joined to the contacts on the first substrate.

2. The method according to claim 1, wherein the silicon wafer is thinned by chemical-mechanical polishing.

3. The method according to claim 1, wherein the carrier plate has a thickness between 100 μ

m and 300 μ

m, and wherein the pores have diameters between 1 μ

m and 10 μ

m.

4. The method according to claim 1, wherein the method further comprises:

providing the entire surface of the silicon wafer with the insulating material after the manufacture of the pores; and

producing the conductive fills from fills that are selected from the group of doped polysilicon, aluminum, copper and amalgam constituents.

5. The method according to claim 1, wherein the method further comprises:

thinning the first substrate proceeding from a second principal surface that lies opposite said first principal surface of the first substrate; and

producing contacts that are electrically connected to components in the region of the first principal surface of the first substrate on the second principal surface of the first substrate.

6. The method according to claim 1, wherein the method further comprises:

securing a second carrier plate that is provided with pores provided with conductive fills substantially in the same way as the first carrier plate, on a first principal surface of a second substrate, the second substrate having components in the region of the first principal surface of the second substrate and having contacts to the components on the first principal surface of the second substrate; and

forming terminal pads that are electrically connected to at least one conductive fill, that meet at least one contact on the first principal surface of the second substrate, and that are joined to said at least one contact, at least on that surface of the second carrier plate adjoining the first principal surface of the second substrate;

thinning the second substrate proceeding from a second principal surface that lies opposite the first principal surface of the second substrate;

producing contacts, that are electrically connected to components in the region of the second principal surface of the second substrate, on the second principal surface of the second substrate;

securing said first carrier plate on the second principal surface of the second substrate such that said first substrate and said second substrate are arranged at opposite sides of said first carrier plate; and

forming terminal pads, that are electrically connected to at least one conductive fill and that meet at least one contact on the second principal surface of the second substrate and that are joined to the at least one contact, on that surface of said first carrier plate adjoining the second principal surface of said second substrate.

7. The method according to claim 6, wherein at least some of the terminal pads of at least one of the first and second carrier plates are structured such that the terminal pads are electrically connected to conductive fills of neighboring pores, so that the terminal pads are connected in parallel.

8. The method according to claim 7, wherein at least one of the first and second carrier plates projects laterally beyond at least one of the neighboring substrates.

9. The method according to claim 8, wherein the laterally projecting carrier plate has at least one terminal contact in the laterally projecting carrier part that is connected via a metallization level to components in at least one of the first and second substrates.

10. A method for manufacturing a cubically integrated circuit arrangement, comprising the steps of:

producing through pores in a doped monocrystalline silicon wafer by electrochemical etching in a fluoride-containing, acidic electrolyte wherein the silicon wafer is connected as an anode;

at least partially providing said through pores with conductive fills, said conductive fills being selected from the group of doped polysilicon, aluminum, copper or of amalgam constituents;

thinning a first substrate proceeding from a second principal surface that lies opposite a first principal surface of the first substrate;

producing contacts, that are electrically connected to components in a region of the first principal surface of the first substrate, on the second principal surface of the first substrate;

securing the silicon wafer, as a first carrier plate, on the first principal surface of the first substrate, the first substrate having the components at least in the region of the first principal surface, the first substrate having contacts to the components on the first principal surface;

forming terminal pads, that are electrically connected to at least one conductive fill and that meet at least one contact on the first principal surface, on a surface of the carrier plate adjoining the first principal surface, said terminal pads being joined to contacts of the contacts on the first substrate.

11. The method according to claim 10, wherein the silicon wafer is thinned by chemical-mechanical polishing.

12. The method according to claim 10, wherein the silicon wafer is thinned by chemical-mechanical polishing.

13. The method according to claim 10, wherein the method further comprises:

securing a second carrier plate that is provided with pores provided with conductive fills substantially in the same way as the first carrier plate, on a first principal surface of a second substrate, the second substrate having components in the region of the first principal surface of the second substrate and having contacts to the components on the first principal surface of the second substrate; and

forming terminal pads that are electrically connected to at least one conductive fill, that meet at least one contact on the first principal surface of the second substrate, and that are joined to said at least one contact, at least on that surface of the second carrier plate adjoining the first principal surface of the second substrate;

thinning the second substrate proceeding from a second principal surface that lies opposite the first principal surface of the second substrate;

producing contacts, that are electrically connected to components in the region of the second principal surface of the second substrate, on the second principal surface of the second substrate;

securing said first carrier plate on the second principal surface of the second substrate such that said first substrate and said second substrate are arranged at opposite sides of said first carrier plate; and

forming terminal pads, that are electrically connected to at least one conductive fill and that meet at least one contact on the second principal surface of the second substrate and that are joined to the at least one contact, on that surface of said first carrier plate adjoining the second principal surface of said second substrate.

14. The method according to claim 13, wherein at least some of the terminal pads of at least one of the first and second carrier plates are structured such that the terminal pads are electrically connected to conductive fills of neighboring pores, so that the terminal pads are connected in parallel.

15. The method according to claim 14, wherein at least one of the first and second carrier plates projects laterally beyond at least one of the neighboring substrates.

16. The method according to claim 15, wherein the laterally projecting carrier plate has at least one terminal contact in the laterally projecting carrier part that is connected via a metallization level to components in at least one of the first and second substrates.

17. A method for manufacturing a cubically integrated circuit arrangement, comprising the steps of:

producing through pores in a doped monocrystalline silicon wafer by electrochemical etching in a fluoride-containing, acidic electrolyte wherein the silicon wafer is connected as an anode;

at least partially providing said through pores, insulated from the silicon wafer, with conductive fills;

securing the silicon wafer, as a first carrier plate, on a first principal surface of a first substrate, the first substrate having components at least in a region of the first principal surface, the first substrate having contacts to the components on the first principal surface;

forming terminal pads, that are electrically connected to at least one conductive fill and that meet at least one contact on the first principal surface, on the surface of the carrier plate adjoining the first principal surface, said terminal pads being joined to the contacts on the first substrate;

securing a second carrier plate that is provided with pores provided with conductive fills substantially in the same way as the first carrier plate, on a first principal surface of a second substrate, the second substrate having components in the region of the first principal surface of the second substrate and having contacts to the components on the first principal surface of the second substrate;

forming terminal pads that are electrically connected to at least one conductive fill, that meet at least one contact on the first principal surface of the second substrate, and that are joined to said at least one contact, at least on that surface of the second carrier plate adjoining the first principal surface of the second substrate;

thinning the second substrate proceeding from a second principal surface that lies opposite the first principal surface of the second substrate;

producing contacts, that are electrically connected to components in the region of the second principal surface of the second substrate, on the second principal surface of the second substrate;

securing said first carrier plate on the second principal surface of the second substrate such that said first substrate and said second substrate are arranged at opposite sides of said first carrier plate; and

forming terminal pads, that are electrically connected to at least one conductive fill and that meet at least one contact on the second principal surface of the second substrate and that are joined to the at least one contact, on that surface of said first carrier plate adjoining the second principal surface of said second substrate.

18. The method according to claim 17, wherein at least some of the terminal pads of at least one of the first and second carrier plates are structured such that the terminal pads are electrically connected to conductive fills of neighboring pores, so that the terminal pads are connected in parallel.

19. The method according to claim 18, wherein at least one of the first and second carrier plates projects laterally beyond at least one of the neighboring substrates.

20. The method according to claim 19, wherein the laterally projecting carrier plate has at least one terminal contact in the laterally projecting carrier part that is connected via a metallization level to components in at least one of the first and second substrates.