Insulated gate semiconductor device and process for fabricating the same

• US 5,530,265 A
• Filed: 08/05/1994
• Issued: 06/25/1996
• Est. Priority Date: 08/12/1993
• Status: Expired due to Term

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Takemura, Yasuhiko
• Primary Examiner(s): WOJCIECHOWICZ, EDWARD JOSEPH
• Application Number:
  US08/286,290
• Time in Patent Office: 690 Days
• Field of Search: 257/51, 257/52, 257/57, 257/66, 257/347, 437/174, 437/228, 437/247, 437/934
• US Class Current: 257/66
• CPC Class Codes: H01L 29/66765 Lateral single gate single channel transistors with inverted structure, i.e. the channel layer is formed after the gate
• CPC Class Codes: H01L 29/78669 with inverted-type structure, e.g. with bottom gate
• CPC Class Codes: H01L 29/78675 with normal-type structure, e.g. with top gate

Abstract

A thin film transistor of reversed stagger type having improved characteristics and yet obtained by a simple process, which is fabricated by selectively doping the semiconductor region on the gate dielectric to form the source, drain, and channel forming regions by using ion implantation, ion doping, or doping a plasma of ions; and then effecting rapid thermal annealing by irradiating a ultraviolet radiation, a visible light, or a near-infrared radiation for a short period of time. The source, drain, and channel forming regions are formed substantially within a single plane.

Claims

1. An insulated gate reverse staggered type MIS semiconductor device provided on an insulating substrate, said insulated gate semiconductor device comprising:

a channel forming region made substantially from an intrinsic amorphous semiconductor; and

source and drain regions made of an N-type or P-type semiconductor having a structural degree of ordering higher than that of said amorphous semiconductor as observed by a peak in Raman scattering spectra;

wherein an ultraviolet radiation, a visible light, or a near infrared radiation is irradiated to said N-type or P-type semiconductor.

2. The insulated gate semiconductor device of claim 1 further comprising a gate electrode coated with an insulator comprising an oxide of a material constituting said gate electrode.

3. The insulated gate semiconductor device of claim 1 wherein said gate electrode comprises tantalum.

4. The insulated gate semiconductor device of claim 1 wherein said N-type or P-type semiconductor comprises a crystalline semiconductor which exhibits structural ordering as observed by a peak in Raman scattering spectra.

5. The insulated gate semiconductor device of claim 1 wherein said N-type or P-type semiconductor is heated by the irradiation of said ultraviolet radiation, said visible light, or said near infrared radiation.

6. The insulated gate Semiconductor device of claim 1 wherein said channel forming region and said source and drain regions are provided in one semiconductor film.

7. The insulated gate semiconductor device of claim 6 wherein said one semiconductor film comprises two or more semiconductor layers.

8. The insulated gate semiconductor device of claim 1 wherein wavelength of 4 to 0.5 μ

m is used for the irradiation of said ultraviolet radiation, said visible light, or said near infrared radiation.

9. The insulated gate semiconductor device of claim 1 wherein said structural degree of ordering higher than that of said amorphous semiconductor is caused by the irradiation of said ultraviolet radiation, said visible light, or said near infrared radiation.

10. The insulated gate semiconductor device of claim 2 wherein said insulator comprising the oxide of the material constituting said gate electrode comprises an anodic oxide.

11. A process for fabricating an insulated gate semiconductor device comprising the steps of:

forming a gate electrode on a substrate;

forming a gate insulating film on said gate electrode;

forming an amorphous or a polycrystalline semiconductor film on said gate insulating film;

providing a masking material on said semiconductor film;

introducing an impurity into said semiconductor film using said masking material as a mask; and

imparting structural ordering to said semiconductor film by irradiating thereto an ultraviolet radiation, a visible light, or a near infrared radiation.

12. The process of claim 11 wherein source, drain and channel forming regions are formed in said semiconductor film.

13. The process of claim 11 wherein said ultraviolet radiation, said visible light, or said near infrared radiation is absorbed by said semiconductor film.

14. The process of claim 11 wherein wavelength of 0.5 to 4 μ

m is used for the irradiation of said ultraviolet radiation, said visible light, or said near infrared radiation.

15. The process of claim 11 wherein said substrate is heated at a temperature of 250°

to 500°

C. during said irradiating.

16. A process for fabricating an insulated gate semiconductor device comprising the steps of:

forming a gate electrode on a substrate;

forming a gate insulating film on said gate electrode;

forming an amorphous or a polycrystalline semiconductor film on said gate insulating film;

providing a masking material on said semiconductor film;

introducing an impurity into said semiconductor film using said masking material as a mask; and

rendering at least a portion of said semiconductor film either P-type or N-type conductive by irradiating an ultraviolet radiation, a visible light, or a near infrared radiation thereto according to said introduced impurity.

17. The process of claim 16 wherein source, drain and channel forming regions are formed in said semiconductor film.

18. The process of claim 16 wherein said ultraviolet radiation, said visible light, or said near infrared radiation is absorbed by said semiconductor film.

19. The process of claim 16 wherein wavelength of 0.5 to 4 μ

m is used for the irradiation of said ultraviolet radiation, said visible light, or said near infrared radiation.

20. The process of claim 16 wherein said substrate is heated at a temperature of 250°

to 500°

C. during said irradiating.

21. A method for manufacturing a semiconductor device comprising the steps of:

forming a gate electrode on a substrate;

forming a gate insulating layer on said gate electrode;

forming a semiconductor film over said gate electrode, with said gate insulating layer interposed therebetween;

forming source and drain regions in said semiconductor film by introducing an impurity into a portion of said semiconductor film; and

irradiating an ultraviolet radiation, a visible light, or a near infrared radiation to activate said introduced impurity.

22. An insulated gate reverse staggered type MIS semiconductor device provided on an insulating substrate, said insulated gate semiconductor device comprising:

a channel forming region made substantially from an intrinsic amorphous semiconductor; and

source and drain regions made of an N-type or P-type semiconductor having a structural degree of ordering higher than that of said amorphous semiconductor as observed by a peak in Raman scattering spectra,

wherein said channel forming region and said source and drain regions are provided in one semiconductor film, and an ultraviolet radiation, a visible light or a near infrared radiation is irradiated to said N-type or P-type semiconductor.

23. An insulated gate reverse staggered type MIS semiconductor device provided on an insulating substrate, said insulated gate semiconductor device comprising:

a channel forming region made substantially from an intrinsic amorphous semiconductor; and

source and drain regions made of an N-type or P-type semiconductor having a structural degree of ordering higher than that of said amorphous semiconductor as observed by a peak in Raman scattering spectra,

wherein light having a wavelength of 4 to 0.5 μ

m is irradiated to said N-type or P-type semiconductor.