Structure capable of simultaneously testing redundant and non-redundant memory elements during stress testing of an integrated circuit memory device

• US 5,530,674 A
• Filed: 04/29/1994
• Issued: 06/25/1996
• Est. Priority Date: 04/29/1994
• Status: Expired due to Term

• Current Assignee: Micron Technology, Inc.
• Original Assignee: SGS-Thomson Microelectronics (STMicroelectronics NV)
• Inventors: McClure, David C., Teel, Thomas A.
• Primary Examiner(s): Nelms, David C.
• Assistant Examiner(s): Tran, Andrew Q.
• Application Number:
  US08/235,161
• Time in Patent Office: 788 Days
• Field of Search: 365/201, 365/200, 365/225.7, 365/230.03, 365/230.06, 365/230.08, 371/21.1
• US Class Current: 365/201
• CPC Class Codes: G11C 11/41 forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
• CPC Class Codes: G11C 29/24 Accessing extra cells, e.g. dummy cells or redundant cells
• CPC Class Codes: G11C 29/50 Marginal testing, e.g. race, voltage or current testing
• CPC Class Codes: G11C 29/70 Masking faults in memories by using spares or by reconfiguring

Abstract

The redundant elements of an integrated circuit memory device having a plurality of redundant and non-redundant elements such as rows, columns, wordlines, and blocks, may be selectively enabled during a stress test mode so that both redundant elements and non-redundant elements may be stress tested concurrently. Enabling capabilities contained within the redundant element circuitry selectively enables the redundant elements when a stress test signal is equal to a predetermined value, indicative of a stress test mode.

Claims

1. An integrated circuit memory device, comprising:

a plurality of non-redundant memory elements, arranged in a plurality of rows and a plurality of columns;

at least one redundant memory element, suitable for replacing a non-redundant memory element that is defective; and

enabling means, coupled to said plurality of non-redundant memory elements and said at least one redundant memory element and contained within a redundant element circuit, for selectively enabling the at least one redundant memory element when a stress test signal is equal to a first predetermined logic level indicative of a stress test mode such that the at least one redundant memory element and the plurality of non-redundant memory elements may be concurrently stress tested when the plurality of non-redundant memory elements are also enabled.

2. The device of claim 1, wherein during the stress test mode the enabling means turns on a plurality of wordlines.

3. The device of claim 2, wherein the plurality of wordlines comprises all the wordlines of the integrated circuit memory device.

4. The device of claim 1, wherein during the stress test mode the enabling means turns on a plurality of columns.

5. The device of claim 4, wherein the plurality of columns comprises all the columns of the integrated circuit memory device.

6. The device of claim 1, wherein the redundant memory element is arranged in a plurality of redundant rows.

7. The device of claim 6, wherein the enabling means is used to selectively enable the redundant rows, and the enabling means is contained within a row redundancy circuit.

8. The device of claim 7, wherein the row redundancy circuit comprises a latchable redundant element.

9. The device of claim 8, wherein the latchable redundant element is placed in a latched mode during the stress test mode, and the logic state of the latchable redundant element is forced to a second predetermined logic level.

10. The device of claim 1, wherein the redundant memory element is arranged in a plurality of redundant columns.

11. The device of claim 10, wherein the enabling means is used to selectively enable the redundant columns, and the enabling means is contained within a redundant column decoder circuit.

12. The device of claim 1, wherein the redundant memory element is grouped into at least one redundant memory array block.

13. The device of claim 12, wherein the enabling means is used to selectively enable the redundant memory array block, and the enabling means is contained within a redundant block decoder circuit.

14. The device of claim 1, wherein the plurality of non-redundant memory elements are grouped into a plurality of memory array blocks.

15. The device of claim 1, wherein the redundant memory element and the non-redundant memory elements are enabled at a pre-repair step.

16. The device of claim 15, wherein enabling the redundant memory element and the non-redundant memory elements at the pre-repair step allows recovery of stress test yield fallout at a repair step.

17. The device of claim 1, wherein the redundant memory element and the non-redundant memory elements are enabled at a post-repair step.

18. The device of claim 1, wherein the enabling means allows for selectively choosing the redundant memory element which is swapped in to replace a defective non-redundant memory element.

19. The device of claim 1, wherein the enabling means is used to control a master redundant enable element for the redundant memory element.

20. The device of claim 1, wherein the redundant memory element and the non-redundant memory elements may be stress tested concurrently.

21. The device of claim 1, wherein the integrated circuit memory device is a static random access memory (SRAM).

22. A method for enabling and stress testing one or more redundant memory elements of an integrated circuit memory device, comprising the steps of:

selectively enabling at least one redundant memory element of the integrated circuit memory device, through an enabling means contained within a redundant element circuit, when a stress test signal is equal to a first predetermined logic level, wherein the integrated circuit memory device comprises a plurality of non-redundant memory elements and the redundant memory element, wherein the plurality of non-redundant memory elements are arranged in a plurality of rows and a plurality of columns, and the redundant memory element is suitable for replacing a non-redundant memory element that is defective; and

concurrently stress testing the redundant memory element and the plurality of non-redundant memory elements when the plurality of non-redundant memory elements are also enabled.

23. The method of claim 22, wherein the redundant memory element and the non-redundant memory elements are stress tested concurrently.

24. The method of claim 22, wherein during the stress test mode the enabling means turns on a plurality of wordlines.

25. The method of claim 24, wherein the plurality of wordlines comprises all the wordlines of the integrated circuit memory device.

26. The method of claim 22, wherein during the stress test mode the enabling means turns on a plurality of columns.

27. The method of claim 26, wherein the plurality of columns comprises all the columns of the integrated circuit memory device.

28. The method of claim 22, wherein the redundant memory element is arranged in a plurality of redundant rows.

29. The method of claim 28, wherein the enabling means is used to selectively enable the redundant rows, and the enabling means is contained within a row redundancy circuit.

30. The method of claim 29, wherein the row redundancy circuit comprises a latchable redundant element.

31. The method of claim 30, wherein the latchable redundant element is placed in a latched mode during the stress test mode, and the logic state of the latchable redundant element is forced to a second predetermined logic level.

32. The method of claim 22, wherein the redundant memory element is arranged in a plurality of redundant columns.

33. The method of claim 32, wherein the enabling means is used to selectively enable the redundant columns, and the enabling means is contained within a redundant column decoder circuit.

34. The method of claim 22, wherein the redundant memory element is grouped into at least one redundant memory array block.

35. The method of claim 34, wherein the enabling means is used to selectively enable the redundant memory array block, and the enabling means is contained within a redundant block decoder circuit.

36. The method of claim 22, wherein the plurality of non-redundant memory elements are grouped into a plurality of memory array blocks.

37. The method of claim 22, wherein the redundant memory element and the non-redundant memory elements are enabled at a pre-repair step.

38. The method of claim 37, wherein enabling the redundant memory element and the non-redundant memory elements at the pre-repair step allows recovery of stress test yield fallout at a repair step.

39. The method of claim 22, wherein the redundant memory element and the non-redundant memory elements are enabled at a post-repair step.

40. The method of claim 22, wherein the enabling means allows for selectively choosing the redundant memory element which will be swapped in to replace a defective non-redundant memory element.

41. The method of claim 22, wherein the enabling means is used to control a master redundant enable element for the redundant memory element.

42. The method of claim 22, wherein the integrated circuit memory device is a static random access memory (SRAM).