Semiconductor storage device including a controller for continuously writing data to and erasing data from a plurality of flash memories

• US 5,530,828 A
• Filed: 06/22/1993
• Issued: 06/25/1996
• Est. Priority Date: 06/22/1992
• Status: Expired due to Term

• Current Assignee: Emergence Memory Solutions LLC
• Original Assignee: Hitachi, Ltd.
• Inventors: Katayama, Kunihiro, Kaki, Kenichi, Tsunehiro, Takashi
• Primary Examiner(s): Gossage, Glenn
• Application Number:
  US08/079,550
• Time in Patent Office: 1,099 Days
• Field of Search: 395/425, 395/375, 395/650, 395/725, 395/430, 395/481, 395/484, 395/727, 365/185, 365/218, 365/900, 365/226, 365/185.29, 365/185.33, 365/185.11, 365/230.03
• US Class Current: 711/103
• CPC Class Codes: G06F 3/0601 Interfaces specially adapted for storage systems
• CPC Class Codes: G06F 3/061 Improving I/O performance
• CPC Class Codes: G06F 3/0611 in relation to response time
• CPC Class Codes: G06F 3/0613 in relation to throughput
• CPC Class Codes: G06F 3/064 Management of blocks
• CPC Class Codes: G06F 3/0656 Data buffering arrangements
• CPC Class Codes: G06F 3/0659 Command handling arrangements, e.g. command buffers, queues, command scheduling
• CPC Class Codes: G06F 3/0664 at device level, e.g. emulation of a storage device or system
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
• CPC Class Codes: G06F 3/0688 Non-volatile semiconductor memory arrays
• CPC Class Codes: G11C 16/102 External programming circuits, e.g. EPROM programmers; In-circuit programming or reprogramming; EPROM emulators
• CPC Class Codes: G11C 16/32 Timing circuits

Abstract

A semiconductor storage device such as a disk pack includes a plurality of flash memories, a write buffer memory in which data are temporarily held, a processor which controls data writing and erasing operations and which transfers and analyzes commands and statuses to and from the flash memories, and a circuit which generates a writing supply voltage Vpp for the flash memories. The semiconductor disk pack may be connected, for example, to a standard bus in a personal computer. The processor operates to send a first instruction for writing or erasing data of one word into a first one of the flash memories, and it continuously writes the data of one word into an accessible one of the other flash memories before the first one of the flash memories becomes capable of accepting the next write or erase instruction. The semiconductor storage device further includes a static random access memory for storing a conversion table for converting logical sector numbers into physical sector numbers for those areas of the flash memories which have accepted the write and erase instructions.

Claims

1. A semiconductor storage device, comprising:

a plurality of nonvolatile memories for storing data therein; and

a processor coupled to provide a plurality of write instructions to said plurality of nonvolatile memories continuously,

wherein said plurality of write instructions, beginning with a first write instruction thereof, is sequentially fed to said plurality of nonvolatile memories in a manner such that each such write instruction is provided to a respective nonvolatile memory, without first having to wait for those ones of said plurality of nonvolatile memories which each earlier received a write instruction taken from said plurality of write instructions, to get ready to accept a new write instruction, said plurality of write instructions being provided to said nonvolatile memories, respectively, after all of said plurality of nonvolatile memories are initially made ready for accepting new write instructions, and

wherein after said plurality of nonvolatile memories has been provided with said plurality of write instructions, said processor determines whether or not those of said plurality of nonvolatile memories which received said plurality of write instructions have become individually ready to accept a new instruction, and said processor provides a new write instruction to respective ones of those of said nonvolatile memories which have been determined to be ready to accept a new instruction.

2. A semiconductor storage device according to claim 1, further comprising memory means for storing therein information of correspondence between logical addresses and physical addresses of those of said nonvolatile memories to be provided with a write instruction.

3. A semiconductor storage device according to claim 1, wherein said nonvolatile memories are flash memories.

4. A semiconductor storage device according to claim 3, wherein each flash memory is comprised of a separate flash memory semiconductor chip.

5. A semiconductor storage device according to claim 1, wherein each of said plurality of nonvolatile memories further comprises a status indicator for indicating, in response to a request by said processor, whether or not that nonvolatile memory is ready for accepting a new write instruction to said processor.

6. A semiconductor storage device according to claim 5, further comprising memory means for storing therein information of correspondence between logical addresses and physical addresses of those of said nonvolatile memories to be provided with a write instruction.

7. A semiconductor storage device according to claim 6, wherein said nonvolatile memories are flash memories.

8. A semiconductor storage device according to claim 7, wherein each flash memory is comprised of a separate flash memory semiconductor chip.

9. A semiconductor storage device, comprising:

a plurality of nonvolatile memories for storing data therein; and

a processor coupled to provide a plurality of erase instructions to said plurality of nonvolatile memories,

wherein said plurality of erase instructions, beginning with a first erase instruction thereof, is sequentially fed to said plurality of nonvolatile memories in a manner such that each such erase instruction is provided to a respective nonvolatile memory, without first having to wait for those ones of said plurality of nonvolatile memories which each earlier received an erase instruction taken from said plurality of erase instructions, to get ready to accept a new erase instruction, said plurality of erase instructions being provided to said nonvolatile memories, respectively, after all of said plurality of nonvolatile memories are initially made ready for accepting new erase instructions, and

wherein after said plurality of nonvolatile memories have been provided with said plurality of erase instructions, said processor determines whether or not those of said plurality of nonvolatile memories which received said plurality of erase instructions have become individually ready to accept a new instruction, and said processor provides a new erase instruction to respective ones of those of said nonvolatile memories which have been determined to be ready to accept a new instruction.

10. A semiconductor storage device according to claim 9, further comprising memory means for storing therein information of correspondence between logical addresses and physical addresses of those of said nonvolatile memories to be provided with an erase instruction.

11. A semiconductor storage device according to claim 9, wherein said nonvolatile memories are flash memories.

12. A semiconductor storage device according to claim 9, wherein each of said plurality of nonvolatile memories further comprises a status indicator for indicating, in response to a request by said processor, whether or not that nonvolatile memory is ready for accepting a new erase instruction to said processor.

13. A semiconductor storage device according to claim 12, further comprising memory means for storing therein information of correspondence between logical addresses and physical addresses of those of said nonvolatile memories to be provided with an erase instruction.

14. A semiconductor storage device according claim 12, wherein each flash memory is comprised of a separate flash memory semiconductor chip.