Computer memory data merging technique for computers with write-back caches

• US 5,530,835 A
• Filed: 09/18/1991
• Issued: 06/25/1996
• Est. Priority Date: 09/18/1991
• Status: Expired due to Term

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: NCR Corporation (NCR Voyix Corporation)
• Inventors: Strickland, Terry S., Vashi, Amit D.
• Primary Examiner(s): Kim, Matthew M.
• Application Number:
  US07/761,609
• Time in Patent Office: 1,742 Days
• Field of Search: 364/200 MS File, 364/900 MS File, 395/400 MS File, 395/425 MS File, 395/200.08, 395/447, 395/448, 395/470, 395/474
• US Class Current: 711/147
• CPC Class Codes: G06F 12/0804 with main memory updating G06F12/0806 takes precedence

Abstract

A memory controller intercepts data bytes destined for a memory and selectively combines them with data bytes previously read from the memory. The controller also blocks data bytes destined for the memory corresponding to data bytes previously written to the memory. The memory controller includes an input device and an output device. An output line of the input device is connected to both the memory and an input line of the output device. Also, the memory is connected to the input line of the output device.

Claims

1. A memory controller comprising:

an input device, connected to a first processor and a second processor, which receives one or more incoming data bytes from the first processor and combines them to form a first data element;

a memory which stores therein a second data element having one or more data bytes, said memory being connected to an output of the input device for receiving the first data element and overwriting a portion of the second data element therewith; and

an output device, connected to the first processor and the second processor, which receives data bytes of the second data element from the memory and data bytes of the first data element from the input device and combines them to form a third data element which is subsequently transmitted to the second processor,

wherein the first processor and the second processor each transfers data to the memory though said input device and receives data from the memory through the output device.

2. The controller of claim 1 wherein a first system bus is connected between said input device and the first processor, and a second system bus is connected between said output device and the second processor.

3. The controller of claim 2 wherein the first processor and the second processor each includes a write-back cache memory for transferring data to said memory through said input device and receiving data from said memory through said output device.

4. The controller of claim 1 wherein said input device is connected to two system buses and wherein said input device includes:

first and second input registers which receive data bytes from said two system buses; and

a first multiplexer, connected between said memory and registers, and having a control input for selecting data bytes from either of said registers.

5. The controller of claim 4 wherein said input device further includes:

a second multiplexer, connected between said memory and registers, and having a control input for selecting data bytes from each of said registers.

6. The controller of claim 5 wherein said input device further includes:

first and second write registers connected between said first and second multiplexers, respectively, and said memory.

7. The controller of claim 6 wherein said input device further includes:

a third multiplexer connected between said memory and first and second write registers.

8. The controller of claim 1 wherein said output device is connected to two system buses and wherein said output device includes:

first and second read registers, each register having a data input line connected to both the memory and output of the input device.

9. The controller of claim 8 wherein said output device further includes:

a control gate, connected between the registers and data input line, for selecting which data bytes appearing on the data input line to latch into an read register.

10. A memory controller comprising:

means for storing a first set of data bytes which are read from a memory, said storing means being connected to a first processor and a second processor;

means for intercepting a second set of data bytes being transferred from the first processor to the memory, said intercepting means being connected to the first processor and the second processor; and

means for overwriting a portion of the first set of data bytes stored in the storing means with the second set of data bytes intercepted by the intercepting means so as to form a third set of data bytes which is subsequently transferred to the second processor.

11. The controller of claim 10 wherein said intercepting means includes an input device connected to said memory for holding the second set of data bytes destined for said memory.

12. The controller of claim 11 wherein said storing means includes an output device having an input line connected to both the memory and input device.

13. The controller of claim 12 wherein said output device has a control gate, connected to the input line, for enabling the interception of each data byte of the second set of data bytes.

14. The controller of claim 13 wherein said input and output device are each connected to two system buses.

15. A method for transferring a data element within a computer system, the computer system having a first processor, a second processor and a system memory, comprising the steps of:

reading a first data element from the system memory into a first register;

transferring a second data element from a cache memory of the first processor to a second register;

obtaining selected bytes of the second data element from the second register to overwrite corresponding bytes of the first data element in the first register so as to form a third data element in the first register; and

reading the third data element from the first register into the second processor.

16. The method of claim 15 further comprising:

determining, prior to transferring the second data element, that said second data element is stored in said cache memory of the first processor.

17. The method of claim 16 wherein said determining step includes comparing an address of said second data element with entries stored in the system memory to determine if said second data element is stored in the cache memory of the first processor.

18. The method of claim 17 wherein said cache memory of said first processor is a second level write-back cache memory.

19. A method comprising:

reading a first data element from a computer system memory into a register;

intercepting a second data element which is being transferred from a cache memory of a first processor to the computer system memory;

overwriting a portion of the first data element with the second data element intercepted in the intercepting step so as to form a third data element in the register; and

reading the third data element from the register into a second processor.

20. A method comprising:

writing bytes of a first data element from a first cache memory of a first processor to a computer system memory; and

writing selected bytes of a second data element from a second cache memory of a second processor to said computer system memory so as to overwrite a portion of the first data element and form a third data element in the computer system memory.

21. A memory controller comprising:

means for storing a first set of data bytes which are read from a computer system memory, said storing means being connected to a first processor and a second processor;

means for intercepting a second set of data bytes being transferred from the first processor to the computer system memory, said intercepting means being connected to the first processor and the second processor;

means for overwriting a portion of the first set of data bytes stored in the storing means with the second set of data bytes intercepted by the intercepting means so as to form a third set of data bytes which is subsequently transferred to the second processor;

means for writing data bytes of a fourth data element from a first cache memory of the first processor to the computer system memory; and

means for writing selected data bytes of a fifth data element from a second cache memory of the second processor to the computer system memory so as to overwrite a portion of the fourth data element and form a sixth data element in the computer system memory.

22. A memory controller comprising:

means for writing data bytes of a first data element from a first cache memory of a first processor to a computer system memory; and

means for writing selected data bytes of a second data element from a second cache memory of a second processor to said computer system memory so as to overwrite a portion of the first data element and form a third data element in the computer system memory.

23. The memory controller of claim 22 wherein said second data element writing means includes:

an input device, connected to the computer system memory, which receives the second data element and writes selected data bytes of the second data element into the computer system memory.